PXIe-6704 Measuring Analog Output Signal

[bennyk]

if the PCL is running the model at 35kHz then i am not sure how i can measure a signal that is 17.5kHz? i would have thought that running the model at 35kHz would result in the output signal being made up of 35kHz datapoints. if i set the PCL to 17.5kHz then i guess i could only measure a sig half that again?

the sine wave i am outputting from my model is at a freq of around 900Hz. this sinewave is coming from the model which is running at 35kHz in the PXIe. I am seeing the waveform in veristand workspace ok, it is steepy but i can see the low frequency dynamics.

the attached waveform is what i am seeing in veristand, the bottom in the interpolated and the bittom is the un-interpolated graph. is there anyway that i can get my oscilliscope to measure this same signal at the terminals on the pxie-6704 card on the chassis do you think? even if there was some filtering technique i could apply maybe or get the pxi to intepolate? is it a case that just becasue i can view this signal in veristand it dosenment mean that i can phsically measure the same out of the physical device?

[bennyk]

i ahve ran further tests and am seeing the following

i have a really simple model of literall a sine wave to an outport. the models sine wave is at 80Hz. i complied this model at 50kHz and at 1kHz and ran both this on the PXI. when i increase the freq of the sone wave above around 100Hz the wave becomes unreconisable as a sine and is very steppy.

the sample period of the digitised sine wave signal when measured on an oscilliscope is 1.8ms (this is 555.5Hz) this is th4e case when both ran at 1kHz and 40kHz. i would expect the sample period to reduce as the PCL freq was reduced? as the model output is calculated at a lower rate? i am using a 6704 card and am wondering if there is a limit of 555.5Hz on its update rate? or something like that?

thanks

brendan