You're right that the oversampling occurs on the device and this data does not get transferred via the PXI backplane. Everything else still applies, however. And I performed some simple mental math and I can agree that this seems to be within the PXI bandwidth, however, I am not a developer and I do not know all the reasoning behind their design choices; I was simply trying to relay some information to you as soon as possible. I think the simple fact remains that this device is intended to be synchronized with other devices in the family, which require the PXIe 100 clock, which is only present on PXIe chassis. I apologize if my information was unclear or irrelevant, but the fact remains that we currently do not have this device in the PXI form factor. I (or Jared) would be happy to relay your use case to the developers. Have a good day!