Is there anyway to set PXI the trigger lines using MAX or 6052E?

[Abhro]

I am trying to have an FPGA module (PXI-7831R) produce a trigger on the PXI bus to begin a pulse generation using DAQMX (6052E) from the rising edge of the PXI trigger. The problem is I have to produce a trigger on the first iteration of a single-cycled-loop on the FPGA monitoring the pulses of an encoder (essentially the encoder count). For some reason, the PXI trigger is high in its idle state, so the first trigger doesn't produce an edge because its a high-to-high transition causing the 6052E to miss the first pulse generation. The option to set the PXI trigger line low from the FPGA prior to entering the loop is out of question, because the FPGA produces a compile error stating that you can't set the line outside the single-cycled-loop. So that leaves me one option, set it in MAX or somewhere else, maybe using the 6052E????

Arindam

[Thaison_V]

Hi Arindam,

I hope you're doing well.  I'd be curious to get more information on the actual compile error that you are receiving and how you have set up your VI to cause it, but in any case, there may be a work-around in the meantime.  Instead of setting the initial value of the line outside of your single-cycle loop, you can use the "First Call?" function (Functions»Programming»Synchronization»First Call?) with a case structure to set the value of your line on the first iteration, and then execute as normal upon other iterations.  You may also be able to do the same with a case structure that checks the iteration count of the loop to see if it equals 0.  Let me know if you have any questions about this.  If you can provide more information about the error (the error number and exact description), we might be able to give more insight.  Have a great day!

Thaison V
Applications Engineer
National Instruments