IPCI device driver development in CVI for RT OS

[Din-o]

I'm writing a driver for a PXI card that uses the 9030 bridge chip for PCI

access. This device needs to be used with the national Instruments( NI )

Labview real time OS( LV RT ) in a PXI instrument rack. I have the WIN32

API driver code for the card and need to redevelop it for LV RT. I need

assistance in the following area: How do the VISA calls to access

Configration space and BAR0 -BAR5 space map to PLX IOPsace0-4  and the PLX

registers on the 9030 chip. In other words; how do I translate a call in

the current driver, lets' say for example a write to an offset into

IOPspace1, to a call that writes to an offset into a particular BAR0-5

space ? Or how I translate a call in the current driver, lets' say for

example a write to an offset into a PLX register( PlxRegisterWrite(...) )

into an offset into a particular BAR0-5 space. I can state the following

facts: I can successfully  read the PCI configuration space registers using

the VISA API ; the VISA API tells me that BAR1 is configured for IO access

with a space of 0x80 bytes; the VISA API tells me that BAR2 and BAR3 are

configured for memory access with a space of 0x1000 bytes. Does this mean

BAR1 translates to PLX register data, and that BAR2 and BAR3 are equivilent

to IOPspace0 and IOPspace01? What's the difference between a BAR space

being configured for memory access, and a BAR space being configured forIO

access?

  Having these cards work in the LV RT OS will be a huge selling point for

NI PXI.

Thanks for any assistance you can provide.
Regards- Dean

[Jason W]

Hello,

Please refer to this forum for discussion about this question.

Thanks,

Jason W.
Application Engineer
National Instruments