07-14-2014 06:54 AM
Good day forum members!
I'm currently designing a PXI-express card whcih must be inserted in a NI PXI-express chassis. I read the documentation and specification of PXI, PXI-express and cPCIexpress, but it appears that I am not able to find any voltage level specification for the GA (Geographical Address pins) which are present in the J4 connector. I must know at least their voltage for high level input before connect them to the FPGA which is onboard. I'd like to avoid to connect a 12 Volt signal directly to a 1.8V Bank of the FPGA. Yes, I know, I can always use a voltage divider (done with resistors) before the FPGA inputs, but I believe is better to know the spcifications before designing than design something wrongly.
Can anybody give a hint?
Many Thanks,
Emanuele
Solved! Go to Solution.
07-15-2014 08:58 AM
Hi Emanuele,
this is the support-forum, so I think your questions can be better addressed by using these PXI-Developer-Resources
http://www.ni.com/white-paper/4756/en/
Marco Brauner AES NIG
07-15-2014 09:35 AM
Thanks for the answer. In the meanwhile I got the idea to check not only cPCIexpress, PXIexpress and PXI specifications but also the cPCI spec where on paragraph 3.2.7.6 is clearly written
"Geographic Addressing (GA[4..0]) For backplanes, if P2 is populated on a particular slot, then it shall support the GA[4..0] geographic addressing signals for unique slot identification. Boards that use geographical address signals GA[4..0] shall be pulled up with a 10.0 KΩ±10% resistor."
I do believe it is valid also for PXI -> cPCIex -> PXIex specifications even if it in NOT clearly written in the PXI-ex spec to go back to 1999, check the cPCI spec to see how connect these 5 pins.
A good example for bad-written spec, imho.
Many thanks again!
07-15-2014 09:35 AM
A more specific answer for your question: the GA pins are either floating or tied to GND. You're expected to pull them up on your board to whatever voltage is appropriate for your device.
- Robert