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[FlexRIO] Getting started with synchronizing multiple sample clocks

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Hello,

 

Previously, I tried reading from two different FlexRIO cards (PXIe-7962R + NI-5734) in the "40 MHz Onboard Clock" or "PXI_Clk10" clock domains. Triggering was done by simply looking for a rising edge on PXI_Trig0:

Simple FlexRIO - FPGA Pack.png

 

 

This produced glitches, but at there was no skew (or at least constant skew) between the two FlexRIOs -- I sent a duplicated pulse train into both cards, and the triggered-acquired waveforms were always in phase: 

Pulses - In Phase.png

 

 

To prevent glitches, I switched to the sample clocks (IO Module Clock 0). Unfortunately, the sample clocks between the two FlexRIOs had nothing in common, so the acquired waveforms were no longer in phase. Even worse, the phase difference changes with every trigger:

Pulses - Out of Phase.png

 

 

Looking at the FIDL Synchronization library's implementation, the conventional technique for synchronizing multiple FlexRIO cards seems to revolve around master-slave synchronization (is my observation correct?). I was wondering: Is there a way to simply share a common sample clock between the cards (like what the 40 MHz Onboard Clock was doing before), as described in http://www.ni.com/white-paper/11369/en/ ? (I think I understand the cons associated with Sample Clock Synchronization, but I'm willing to try it for now).

 

Thanks in advance!

Certified LabVIEW Developer
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Hi JKSH,

 

Page 9 in the 5734 manual describes the different clocking methods that can be used the 5734. You can either synchronize each module's sample clock to a clock available through the backplane of your chassis (such as DStar_A) by enabling IOModSynClk in the 5734 properties (available the details category) or use an external clock coming in through the Clk In port on the module. Enabling IOModSyncClk is probably the easiest approach and will result in the sample clocks on each IO module being PLLed to the common clock - which should synchronize the two sample clocks together.

 

Let me know if you have any follow-up questions.

 

Regards,

Ryan K.
Product Manager, ATCA and BEEcube
National Instruments
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Just to clarify, the 573x modules will by default use an internal osciallator to generate the sample clock and will not PLL that to any reference CLK. If you look at the Clock Select example in the example finder you'll see how to configure the different clocking options for the FAM.

 

The option you probably want is "Internal Clock PLL On (IoModSyncClk)". This will PLL the sample clock to the PXI CLK10 so long as the PXI CLK10 has been routed across the IoModSyncClk line (right click the FAM in the project and select properties, then go to the details category).

 

 

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