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FPGA/FPGA Adapter creates 250mV voltage offset

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I am running a PXIe-7971R FPGA in a PXIe-1073 chassis with the 5782 Adapter Module (DC-coupled) and the 2016.08 Device Drivers. When I turn on the chassis and my computer, nothing odd happens. When I try to run something on the FPGA, however, things get weird. Every piece of the code works just as it should, but as soon as "FPGA Open Reference" finishes running the adapter starts producing a +250 mV voltage at AI 0 and AI 1. This does not happen for AO 0 or AO 1. This voltage offset goes away temporarily for as long as "FPGA Open Reference" or "FPGA Close Reference" are running, but the only way to get rid of the voltage offset entirely is to restart the chassis. Can someone explain to me why this is happening and how to fix it? The FPGA code I'm running can handle a small offset, but this offset appears to be saturating the signal.

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Hi ForrestBarnes, 

 

How are you determining/seeing this offset? Could you attach some screenshots of what you are seeing? 
Is the offset there for any VI or one in particular?

Also, are you using a shipping example or is this a program you wrote yourself? 
If possible, it would be helpful to see the block diagram if you could either attach the VI or a screenshot of that. 

Shalini M.
Partner Development Engineer
Alliance Partner Network
National Instruments
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To see the offset: instead of plugging AI 0 and AI 1 into my detectors I plug AI 0 and AI 1 directly into a 1M terminated oscilloscope.

The offset appears to begin when I run any vi that calls "Open FPGA Connection" and only goes back to 0 when either "Close FPGA Connection" or "Open FPGA Connection" is running. I have tried 3 VIs (each of which reprograms the FPGA with its own custom code). My next step will be to see if the problem persists even after my computer is shut down.

The VIs I run are my own. The most basic is shown below, with its FPGA code. I will be modifying this soon to enhance my testing ability, and post more results as I get them.

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Can you send a wiring diagram of how you have everything set up? 


Also, what exactly do you mean by "only goes back to 0 when either "Close FPGA Connection" or "Open FPGA Connection" is running"? Are you using highlight execution to determine this or is it only when the while loop is executing that you see the offset? 

 

Finally, can you try running the 5782 getting started shipping example and let me know if you see the same behavior? 

Shalini M.
Partner Development Engineer
Alliance Partner Network
National Instruments
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Solution
Accepted by topic author ForrestBarnes

To see the offset:  I plug AI 0 and AI 1 directly into a 1M terminated oscilloscope.

Thats expected. The ADC on that FAM (and most high end ADCs) have a sampling range that isn't centered around zero. The front end of the FAM compenstates for this by applying an offset to the signal that would make it appear to a user that the range of the ADC is centered around zero. What differs between this FAM and other instruments is that there isn't additional circuitry that prevents this offset from being observed when a user measures the output of the analog input.

 

The reason you see the offset occur at Open FPGA Reference is because that's when power to the FAM is enabled. The offset shouldn't have any effect on the reading that the analog input provides. Just make sure you've impedance matched the signal source to the analog input and you should be good.

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Thank you. The inputs are actually centered near 125 mV for some reason, but we've figured out how to get the setup to work with a few modifications.

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