11-13-2014 10:22 AM
Hello All,
I have a SubVI that uses block memory, which has been created using Xilinx "Block Memory Generator 8.1". I have configured this block memory to be a "Single Port ROM", and I use a coefficient file to initialize the memory contents. In simulation mode, everything works as it should.
Next, when I try to compile the top-level VI, I get the following error:
http://www.cs.nyu.edu/~aditya/Compilation_Log_100.txt
http://www.cs.nyu.edu/~aditya/Dividing (This is the coefficient file)
Essentially, the compiler is looking at an ill-formed path to find the coefficient file.
My environment:
-- LabView 2014 f1 (32 Bit)
-- FPGA module 2014
-- RT Module 2014
-- Xilinx Vivado 2013.4
-- NI RIO Drivers 14
-- Development Machine and Conpile Server: Windows 7 Professional, 32GB RAM
-- Compile Worker running Linux, with Xilinx Compile tools installed
Is this a bug, or am I doing something wrong? Thanks!
Best,
Aditya
11-13-2014 11:00 AM
Next, I tried compiling on the windows machine itself. And here is the error that I get. (See attached image).
Thanks!
best,
aditya
11-18-2014 02:11 PM
Aditya,
Can you give us a better idea of both how you are implementing this IP into your LabVIEW VI and how you attach the coe file to it. This is Xilinx IP so I do not know how it is working, but if we get an idea of how you integrate this with LabVIEW we may be able to help.
12-03-2014 09:33 AM
Hello Matt,
Thanks for your response.
I add the "Block Memory Generator 8.1" block to my block diagram. Double click it, and a window pops up. In this window, click on the "Other Options" tab. Under "Memory Initialization", select the "Load Init File" option, and click on "Edit".
In the COE file editor, enter the values. For example, enter "10" under "memory_initialization_radix", and enter 9,8,5 as the vector. Validate and save.
When attempting to compile the top level VI, it fails as described earlier.
Thanks again!
best,
aditya