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External Clocking of NI 5782 with PXIe-6674T

Is there any example code that demonstrates using external sample clock NI 5782 either through

1) External Sample Clock through IoModSyncClock (A capability mentioned in on page 9 of NI 5782 user manual). Or,

2) External Sample Clock through the CLK IN connector (A capability mentioned in on page 9 of NI 5782 user manual)

 

In both the option my sample clock source would be PXIe-6674T and FlexRIO used is PXIe-7966R.

 

I was looking for example other than those in the clock select example. They don't behave as expected. Atleast that's what I observed. Moreover its not integrated with PXIe-6674T. I was looking for an integrated example. One simple feedback, when you generate 125MHz and feed it to the clk in of 5782, I found no. of sample representing one cycle of a 1MHz input signal is about 30 samples whereas it should be 125samples. Secondly, no indication or documentation/ instruction on how to get IOModulesync routed to NI5782 as sample clock specially with PXIe-6674T. 

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Message 1 of 11
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Hello Blore,

 

Thank you very much for the feedback. I am sorry that the examples did not behave as your expected.

 

I recommend using the 5782 - Clock Select Example, which you have already found. This example includes options to use IOModSyncClk as a Reference of Sample Clock. On the FlexRIO's IO Module Properties >> Details windows, you can select the source of the IOModSyncClk. Using the 6674T API, 6674T Example, or MAX Test Panel, these clocks can be overwritten by the 6674T.

 

For example if I wanted to use an External Sample Clock of 400MHz, I would do the following:

1) Open the 5782 - Clock Select Example
2) Open the target FlexRIO's IO Module Properties and select IOModSyncClk Enable and PXIe_DStarA
3) In the Host VI, External Clock (IOModSyncClk)
4) Using the 6674T API, Example, or Test Panel, I would route the DDS to the DStarA Line and set the Frequency to 400MHz
5) Run the Host VI

 

As far as the incorrect number of samples using your external sample clock, this could be due to the CLKIN Limitations of the 5782 (250 - 1000MHz).

 

Can you please give the above a try and let us know the results?

 

I agree with you, there is a lack of documentation on utilizing the IOModSyncClk. I will make sure that more is made.

 

Regards,
Tom

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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Hi Tom,

Thanks for your response. But all the points you have mentioned (with 400MHz) was tried out at 125MHz. But the example code throws out an error. I guess this error is due to the DSTARA and IOModsynclk doesn't gets connected. 

 

Secondly, in we use external CLKIN it work only till 220MHz (strange!!!). 250-1000MHz is ruled out.

 

Look our main objective is we have two NI 5782 modules. We are getting syncronisation between channel to channel but the same synchorisation is not evident between module to module even if we trigger start the two acquisition loops. This is due two NI5782 running with its own data clock provide by the CLIP. 

 

We want all the four channel to be synchonised therefore it should run with a single sample clock. We thought it is should be possible by means of below two possibilities

1) External Sample Clock through IoModSyncClock (A capability mentioned in on page 9 of NI 5782 user manual). Or,

2) External Sample Clock through the CLK IN connector (A capability mentioned in on page 9 of NI 5782 user manual)

 

 

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Hello Blore,

 

Strange indeed.

 

Can you post screenshots of the errors you are receiving?

 

Can you please clarify if you have changed the IO module Properties?

 

What happens when you increase the CLKIN above 220MHz? Is there an error?

 

I recommend using the IoModSyncClock. It will save you a few cables.

 

What FlexRIO FPGA Module are you working with?

 

If you want tight synchronization, I recommend looking at the Sync IDLs for FlexRIO:

https://decibel.ni.com/content/docs/DOC-15799

 

This contains advanced trigger alignment.

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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1. IOModSyncClk configured to PXI_Clk10 in the project and compiled

a)      we have used default PXI_Clk10 clock, oscillator of 6674T routed to PXI_Clk10In terminal

b)      Synchronisation Clock Source for PXI trigger lines was also set to both above options, PXI_Clk10/Oscillator

c)      Triggering of transfer of data to Host FIFO is done through DSTARB in FPGA, and DSTARB is triggered using Global Software trigger function of 6674T. (Of course Global Software trigger is routed to DSTARBn where n is the star connection of two slots on chassis(1085) hoisting 7966Rs and 5782s)

d)      Configured the Clock Source of 5782 Clock select.vi to Internal Clock PLL On (IOModSyncClk)

Result: there is a mismatch of signals between cards by one or two samples. (70MHz signal acquired at 250MS/s) lead or lag

We really doubt PXI_Clk10 is getting routed to IOModSyncClk or DSTARB is reaching the cards at the same time.

2. IOModSyncClk configured to DSTARA clock in the project and compiled

a)      DDS Clock was set to 400M/125M/250M/500M

b)      Routed the DDS clock to DTARAn lines. Where n is the star connection of two slots on chassis hoisting 7966Rs and 5782s

c)      Configured the Clock Source of 5782 Clock select.vi to External Clock (IOModSyncClk)

d)      Triggering the acquisition was done same as case 1

Result: Error -8999, PLL could not lock within the specified time out.

3. IOModSyncClk configured to DSTARA clock in the project and compiled

a)      DDS Clock was set to 10M

b)      Routed the DDS clock to DTARAn lines. Where n is the star connection of two slots on chassis hoisting 7966Rs and 5782s

c)      Configured the Clock Source of 5782 Clock select.vi to Internal Clock PLL On (IOModSyncClk)

Result: are same as case 1 may be worsened phase mismatch.

4. IOModSyncClk configured to PXI-Clk10 clock in the project and compiled

a)      DDS Clock was routed to CLK OUT terminal of the 6674T

b)      Clock_Out was connected to Clk In terminal of 5782

c)      DDS Clock was set to 80 MHz to 500MHz

d)      Configured the Clock Source of 5782 Clock select.vi to External Clock (CLK IN)

Results: upto 220MHz of DDS Clock samples were being acquired with the results mentioned in the earlier post. Above 220MHz, error -8999 PLL Could not lock within the specified timeout

We might not want to use case 4 unless we can find a solution in case 1 to 3

We are using 7966Rs. The synchronisation in FIDL uses CPTR during the absence of a reference clock. Plus it uses PXI_TRIG lines. I don’t understand why we would need it when we have synchronisation module such as 6674T, which access PXIe Trigger lines as well as clock routing capabilities. Shouldn’t this make the in-chassis modules tightly synchronised?

PS-7966Rs are placed on Slot 9 and slot 13. 6674T is placed on slot 10. (DSTARA/Bn are DTARA/B0 and DSTARA/B11 which corresponds to slot 9 and 13 of 1085 Chassis)

Triggering of transfer of data to host is done as mentioned in case 1 section d. Data was acquired by clearing the buffer in the FIFOs and resending the triggers and acquiring the first set of data after the trigger. This data was compared and the results are leading or lagging by up to 2 samples.

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Hello Blore,

 

You have a good point about using the 6674T.

 

In order to achieve the best synchronization I recommend the following:

1) Outputting the Sample Clock on the DStar Line. The PLL error you are receiving is due the Timebase Clock Class. I have attached an improved Clock Select VI, which allows you to configure it easily. The fault is set 1GHz.

2) Using the Single Sample CLIP instead of the Multi Sample CLIP. This will remove any indeterminism on reading the Trigger caused by the Clock Divider.

 

 

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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Could you please send the VI is LV2013.

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Message 7 of 11
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2013 Version

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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The below are the observations using the improved clock select VI (which Thomas Posted in ni community) for acquisition, using External Clock (IOModSyncClk) option.

  1. The Clock select VI still throws PLL Lock error (error -8999), because of which acquisition wasn't happening.
  2. Now out of frustration 🙂 innovative idea came. Clear the error that originates from Clock Select VI, then acquisition of the signal happened but still there was no tight synchronization. (1MHz signal acquired, which mismatches by 4 to 6 samples)
  3. Using multi- sampled CLIP and External Clock(IOModSyncCLK) there is no tight synchronization.
  4. Even after using Single sampled CLIP and External Clock(IOModSyncCLK) there is no tight synchronization.


All the above observations are done by generating 1GHz clock using DDS and DDS clock is routed to corresponding DstarA lines.

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Hello Blore,

 

This updated VI should fix the PLL error.

 

How are you determining the Sample Offset?

Are you using the Extract Single Tone VI to determine the phase offset between the AI channels?

How are you processing the trigger on the FPGA?

How are you routing the Software Trigger?

Is the channel skew always consistent?

 

 

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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