You need to change a few things in your program:
1) Change your main loop from a timed loop to a regular while loop
2) The inner loop, that is doing the divison, needs a shift register on input X (numeriator) and the output of the subtraction.
3) The remainder tunnel comes from the shift register on the left side of the while loop.
Essentially, you need your divide loop to be more similar to the example you linked.
I've included a VI that works to divide on the FPGA, which is almost identical to the orignal example you linked.
