System Components:
- PXI-1036 chassis connected vi MXI-Express to a laptop
- PXI-6652 Timing and Synchronization Control module
- PXI-6115 S-Series Multifunction DAQ
- PXI-5412 Function Generator
I want to use the 6652 to improve the timing accuracy of the FGEN and AI sampling from the 6115.
- The chassis clock and 5412 on-board clock, have accuracy of +/-25ppm.
- The 6115 timebase has an accuracy of +/- 0.01% (100ppm).
- The 6652 has an initial accuracy of +/-2.5ppm, plus long term and temperature stability of +/-1ppm and +/-2ppm respectively, or roughly an order of magnitude improvement over the other devices.
The 1036 chassis has a switch (S1) to choose between "BP ENABLE" and "SLOT2 ENABLE" for the PXI_CLK10 signal shared with all the modules. I have set this switch to "SLOT2 ENABLE."
Based on this Knowledge Base article (Can my S Series Device Synchronize its Timebase to the 10 MHz Clock on... the 6115 will phase-lock to the chassis 10 MHz backplane clock at power up.
The trouble is that the 10 MHz backplane clock is not present at power up. I've set the switch to replace the chassis clock with the Slot 2 (6652) clock, but I then have to configure the 6652 to export its TCXO oscillator to the PXI_CLK10_IN through software, which obviously happens AFTER power up.
- Have I made any mistakes in my understanding outlined above?
- What does the 6115 phase-lock to if there is no backplane clock at power up?
- Can the state of the phase-lock be read in software?
- Can the phase-lock be re-initiated in any way once I've got the 6652 clock onto the chassis backplane?
