This is not officially specified for the digital FlexRIO modules, but the propogation delay is dependent on the internal circuitry of the module. If you have a module available, testing it in your own setup is the most accurate way of determining this delay.
If you would like to take a look at the voltage line buffers for the 6583, they are the TI SN74AVC2T245. The buffers will determine the majority of the delay that you will see in the 6583 module.
In general, it seems that a reasonable guess will be that the propogation delay will range from 20-50 ns depending how the module is being used.
Thanks for your response, but I'm still a little confused. I looked at the datasheet for the buffers and it says that its max prop delay is only about 4 ns. And your estimate was in the 20-50 ns range. Where does all that extra delay come from?
Also do you have any suggestions on how to measure the prop delay in our own setup? How would we access the internal pins to be able to compare the input edge to the output edge of the module?
The estimates come from some basic testing done here, as well as speaking with some engineers that are familiar with the hardware delays that you might see. There is a lot that plays into the actual delay you will see and it can be very different depending on the application.
Do you mind explaining the application and why you are looking for these numbers? The reason I ask is that it typically isn't something that comes into play in most applications without a specific reason behind it, such as attempting to determine the absolute time for a system to perform a task.
Are you using some sort of feedback loop? Is the application going to be hardware or software timed?
Thanks for providing the feedback Cody. Let me know if you have further questions.
We're trying to implement SPI communcation through the FPGA in a 7954R, but there's a strange problem when trying to recieve data at clock frequencies beyond about 10MHz. We're generating an internal clock, and outputting it to the the part through the 6583 module. But when we receive data back, we miss the first bit, but then all the other following data in that vector is correct. So it seems the data just shifts by one bit. Our thought was that since the internal state machine for receiving data is triggered off the same clock edge as the clock we're putting out to the part, if there was a significant enough delay for the clock and data to propagate through the 6583 module, we would miss a bit and our data would be shifted, like we are seeing. And a prop delay on the order of 30ns would be enough to cause that.
Does that seem like a reasonable theory?
I think that is a pretty reasonable theory, considering your setup. What probably makes sense is to attempt to compensate for the delay in one way or another. Two ways that I would suggest:
If you have questions or want more detail on one of these methods, let me know!
For all interested in this issue, there are a few updates that may help users pursuing similar applications.
Through testing, a NI customer was able to implement 100MHz SPI communication with the 6585 FlexRIO Adapter Module. They were able to compensate for the propagation delay by adding compensation delay in the FPGA code.
The customer accomplished this by delaying when the Master device reads the MISO line (the delay was increased in half-period increments) until this compensation matched the propagation delay.
The customer saw delays between 20-25ns with a SHC68-68-S cable. With a 1 meter cable, the delay compensation was between 30ns and 35ns. These benchmarks should give users a ballpark figure of what delays to expect.
Additionally, there is a new product, the NI USB-8452 OEM, that will do 50MHz SPI communication. This might be useful for customers that want an all-in-one SPI solution up to 50MHz.
Have you seen these tutorials from NI Developer Zone?
Implementing SPI Communication Protocol in LabVIEW FPGA
Simple SPI Communication with LabVIEW FPGA and the PXI-7831R
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