Hi Everybody!
This week I would like to talk about a very important and unique feature of FPGA programming; the Single-Cycle Timed Loop.
The Single-Cycle Timed Loop (SCTL) is the FPGA version of the Timed Loop that you see in Real-Time programming. It is very useful because it allows us to perform multiple operations within a single tick of the FPGA’s clock. Please refer to the link below.
Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module)
So if we are using the default 40 MHz clock as our Top-Level Clock, each tick (or clock cycle) will take 25 ns to execute. In the example above, that means it would take 100 ns to execute the code inside the while loop (excluding the 2 ticks of overhead for the while loop). By placing that code inside an SCTL, it only takes 25 ns!
Unfortunately, we cannot just place all of our code inside an SCTL. If you try and place too much code in a single combinatorial path inside the loop, you may get a timing violation, which means that compiler cannot fit all of that code into a single tick. There are several ways to fix the timing violation, but some of the easiest ones are to either reduce the clock speed by deriving a slower clock, or by parallelizing the code with a technique called pipelining. Below is another great resource for learning how to optimize FPGA code.
Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining
If you have any questions about Single-Cycle Timed Loops, please feel free to post them here!
Best,
Jeff S
Jeff S.
National Instruments
