Data acquisition

[Harss]

Hi,

My application needs me to acquire data at a continous rate of 1MS/sec . I am using a NI cRIO 9030 controller and NI 9223 for data acquisition. I am using 'User controlled I/O Sampling'  VI to acquire the data from the Labview 2014 examples section.I am facing the following difficulties

1:The User controlled I/O sampling does not allow me to continously acquire data . I experience frequent time outs on the FPGA side . On further analysis what I feel is that the DMA FIFO is not getting cleared as fast as it should on the host side . This causes the timeouts on the FPGA VI.I feel the issue could be due to following reasons

1:No enough storage space to store the acquired sample values(maximum samples which are acquired is around 4000000)

2:Need an architecture to clear the DMA FIFO quickly from the host side.

2:I further need to time stamp these acquired samples with an accuracy of microseconds. I am not sure how to use the NI Time Sync FPGA timekeeper VI to accomplish this task , by integrating the timestamping VI with the basic 'User controlled I/O sampling' acquisition VI.

I am new to Labview FPGA and I need an urgent help on this.

Please help!!

Thanks in advance

Regards

[Harss]

Hi,

Please note the second question refers to the GPS timestamping and I am using NI 9467 for the GPS timestamping.

I checked this post http://forums.ni.com/t5/Real-Time-Measurement-and/CRIO-Save-to-Memory/m-p/815285?requireLogin=False recently, will streaming help me any ideas/suggestions pls.

Thanks.

Regards

[Harss]

Hi,

I am acquiring data at the rate of 1MS/sec using NI 9223 and cRIO 9030 controller . I use DMA FIFO for data acquisition . The architecture used is the 'User Controlled I/O Sampling' as mentioned in the Labview 2014 examples section.

I want to timestamp at microseconds resolution using NI 9467 . Is it possible to integrate the acquisition VI with the 'NI Time Sync FPGA timekeeper VI'.Ihave this specific question because I am really new to Labview FPGA and none of the posts in the discussion forum seems to highlight this approach.

I need an urgent help and would be grateful if anybody could help.

Thanks

Regards

[Aix-La-Chapelle]

Hi Harss,

I recommend calling NI support for urgent help.  Additionally, I would recommend that you post to our community forums which have a wider reach, this forum is specifically for users of the LabVIEW RIO Eval Kit, so there's less expertise for overall system approaches such as the question that you have.

Matt

[KHartley]

Harss,

The fpga timekeeper with the NI 9467 has an intended use case of time stamping data at acquisition on the fpga. If all your samples are taken at the same time and are passed directly to the DMA fifo one option is to include the time stamp in the data (preferrable in the same order). You must typecast the data to the same data type as the fifo but when you receive the data you can reverse the operation to get a readable time stamp. The behavior is called interleaving.

Here is a simple example that can run in a single vi. To run this with FPGA you would split each side to interleave the data on fpga, de-interleave the data on RT, and the DMA FIFO is transferring data between the two sides as a black box of sorts.

https://decibel.ni.com/content/docs/DOC-15034

How do I use FPGA Time Keeper with the NI 9467?

http://digital.ni.com/public.nsf/allkb/EFDC35727D4F2CC086257A0700693003?OpenDocument

If you haven't already, I suggest downloading the FPGA Time Keeper here. It comes with several examples of using the time keeper.

https://decibel.ni.com/content/projects/ni-timesync-fpga-timekeeper?view=overview

[Harss]

Hi,

Thanks a lot for the response . I will post it on the community forum.

Regards,

Harshit D.

[Harss]

Hi,

Thanks a lot for the prompt response.

I am carrying out the data acquisition using 'User Controlled I/O Sampling'. Since this is the configuation which allows NI 9223 to sample at the high rate of 1 MS/sec.I have attached the code for your reference .I apologize for the code not being very clear because currently  the cRIO is not connected.

Could you please provide any hints how to integrate the Time Sync VI with this. I just checked out on the interleaving process would this also help me to synchronize between the acquired sample and the corresponding timestamp in microseconds on the host VI because I need to resolve both the components the acquired sample value as well as the time stamps into its corresponding components.

Can you please further provide clarification on this?

Thanks in advance.

Regards.

[KHartley]

Harss,

Here is a snippet, Basically the timekeeper should run in a seperate loop and you use a local variable to pass the timestamp to your dma fifo. Then pass that up to RT and basically need to read multiple of 2 elements to remove the current timestamp and the sample.

[Harss]

Hi Kyle,

Thanks a lot for your reply.

I will definetly try to incorporate your solution and get back to you.

I have attached the snapshot of the code which I just tried today. However, I feel I have just lost the hang of it.

and am unable to understand how the timestamping interface actually works in this case. If you dont mind could you please further provide additional details from your snap shot.

I would be really grateful if you could help me.

Thanks .

Regards.

[Harss]

Hi,

I forgot to mention one fact both the block diagrams are placed on the same FPGA VI.

I did not change anything on the host VI.It was similar to the original 'User Controlled I/O Sampling' process.

I am also not quite clear about the positioning of the 'Synchronize to GPS - cRIO VI' in the snapshot attached by me in my previous response. I am using NI 9467 for GPS timestamping and was not quite clear about the positioning of the 'Synchronize to GPS - cRIO' VI in my case.

I just happened to open the second snapshot today and it seems I didnt upload the updated one, what I tried to do in the DMA Write was I used two DMA writes . The first one for the acquired sample value and the second one from the Get Time.VI from the FPGA timekeeper. The second DMA Write is missing in my snapshot . I will try to take the updated snapshot and send it to you as soon as possible.

Please let me know if you need any more details.

Thanks.

Regards.