reflective memory setup in Veristand

[pmac]

The module in slot 6 is a PXIe-4300 Analog Input. The device pinout in the User Manual shows PFI0 and PFI1 so I changed the Trigger line from PFI5 to PFI1. I now get this error when I deploy:

Thanks,

PatM

[StephenB]

When you get a deployment error it is much more helpful to just post the text rather than a screenshot of the deployment dialog. that way we can see the error code and the full deployment process. Simply copy paste it in here.

I'm not sure what would be reserving that PFI line. unless you are also using it somewhere else in your ni veristand configuration. can you post your system definition so I can look at it?

also, i noticed you're using NI VeriStand 2011 and 18 slot PXI chassis. have you gone into MAX and routed triggers away from the trigger bus segment containing the chassis master device (the 4300 in this case)? In order for hardware timing to work in an 18 slot chassis you must do this. NIVS 2012 does this automatically but 2011 and prior do not. Simply go to max, browse to the chassis, select triggers tab at the bottom, and select the drop down box for the first trigger line (line 0) to route away from the segment containing your chassis master DAQ device.

[pmac]

I have PXI_Trig0 routed away from Slot10 on the Controller chassis but all set to "Dynamic" on the Controller 2 chassis. I changed that to "Away from Slot1" and redeployed. Here is the text from the deployment and resulting error - also, SDF is attached as a zip file.

Thanks

• Initializing TCP subsystem...
• Starting TCP Loops...
• Connection established with target Controller 1.
• Connection established with target Controller 2.
• Preparing to synchronize with targets...
• Querying the active System Definition file from the targets...
• Unloading System Definition file...
• Connection with target Controller 1 has been lost.
• Connection with target Controller 2 has been lost.
• Loading System Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2011\Projects\MOD 120 Projects\120 Dyno Controller.nivssdf
• Preparing to deploy the System Definition to the targets...
• Compiling the System Definition file...
• Initializing TCP subsystem...
• Starting TCP Loops...
• Connection established with target Controller 1.
• Connection established with target Controller 2.
• Sending reset command to all targets...
• Preparing to deploy files to the targets...
• Starting download for target Controller 1...
• Opening FTP session to IP 10.10.10.4...
• Processing Action on Deploy VIs...
• Gathering target dependency files...
• Downloading 120 Dyno Controller_Controller 1.nivsdat [1601 kB] (file 1 of 5)
• Downloading PXIe-433x Timing Source.vi [25 kB] (file 2 of 5)
• Downloading Inertia RT Engine.llb [9257 kB] (file 3 of 5)
• Downloading Embedded Data Logger - Engine - PharLap.llb [1400 kB] (file 4 of 5)
• Downloading Pharlap System Monitor Engine.llb [331 kB] (file 5 of 5)
• Closing FTP session...
• Starting download for target Controller 2...
• Opening FTP session to IP 10.10.10.3...
• Processing Action on Deploy VIs...
• Gathering target dependency files...
• Downloading 120 Dyno Controller_Controller 2.nivsdat [1374 kB] (file 1 of 4)
• Downloading PXIe-433x Timing Source.vi [25 kB] (file 2 of 4)
• Downloading Embedded Data Logger - Engine - PharLap.llb [1400 kB] (file 3 of 4)
• Downloading Pharlap System Monitor Engine.llb [331 kB] (file 4 of 4)
• Closing FTP session...
• Files successfully deployed to the targets.
• Starting deployment group 1...
• Deployment group 1 is ready.
• Starting deployment group 2...

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -89126 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:

Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to

System.vi

Possible reason(s):

Trigger line requested could not be reserved because it is already in use.

=========================

NI VeriStand:  HP Loop.lvlib:HP Loop Main.vi<append>

Property: SampClk.OutputTerm

Destination Device: PXI2Slot6

Task Name: PXI2Slot6_AI

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Unloading System Definition file...
• Connection with target Controller 2 has been lost.
• Connection with target Controller 1 has been lost.

[StephenB]

Hmm. I dont see anything wrong. Your sysdef is set up fine.

Can you get me two more pieces of information:

1. Use your web browser to go to http://<ip address of your controller> for each controller and then go to the console page. That way you can see the console text from the targets while you deploy. If they show an error can you copy paste it here
2. Can you screenshot the trigger settings for each target's chassis? The error indicates trigger 0 was already reserved when PXI2Slot6 tried to use it, which is unexpected.

Some troubleshooting steps as well:

1. Try right click disabling the 433x custom device you have on controller 2. it shouldn't be intereferring but I'm interested to see if disabling it has any effect
2. If #1 has no effect, also try right click disabling all DAQ devices (right click DAQ -> disable all) and then re-enable PXI2Slot6. So it is the only one enabled.

[pmac]

The console viewer revealed several errors. I couldn't see a way to copy the text so I took screnshots which are contained in the attached file along with the trigger settings screenshots.

The troubleshooting steps generated the same error pasted in my last post.

Thanks

[StephenB]

On chassis1 it is very strange that you get an error -88717 when you boot. The system initialization option for the attached sysdef you provided is "wait for deployment". So NI VeriStand should not be attempting to start your sysdef after a reboot... but indeed it is. Are you sure you attached the same system definition that you are actually using? In the NI VeriStand project explorer right click the system definition and select explore.

For the -200022 error on controller 1, you are receiving that error because PFI0 is already reserved by your digital in task. Looking at your system definition you have every AI, AO, CTR, and DI available on this card added. Do you actually need every line for your testing? If not, remove some to increase system performance. You should at least remove Port 1 Line 0 as that is PFI0 and therefore conflicting with your chassis configuration of using that line to export a start trigger.

For the errors on controller 2, it appears that the PXIe-4300 is failing to route its sample clock to the backplane because it says that line is reserved. This is independent of the triggers. Can you double check your controller 2 chassis' trigger configuration in MAX? What chassis do you have? Are you sure PXI2Slot6 is actually in slot 6? Can you screenshot MAX?

[pmac]

I checked and the correct SDF was attached.

Right now, the DAQ in PXI1Slot10 is there only as a Master Hardware Sync Device. So, I guess I only need a single AI channel for that purpose. I deleted all but one AI channel.

I checked the trigger routing for each chassis in MAX and I have them routed correctly but I also had the source bus checked which could be the reason for the conflicts since this reserves the trigger line. I unchecked the source bus in each chassis routing and redeployed the SDF. It now appears that there are no more trigger conflicts but the deployment times out with an error implying that it was waiting for a trigger that never arrived (see below). This suggests that I don’t have the two chassis’ cabled properly.

What physical connections do I need to make to get the exported trigger line to the imported trigger line? There is a pin on the front of each controller (PXIe-8133) labeled “trig” is that the connectors I  need to tie together?

Deployment Text:

em Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2011\Projects\MOD 120 Projects\120 Dyno Controller.nivssdf

• Preparing to deploy the System Definition to the targets...

• Compiling the System Definition file...

• Initializing TCP subsystem...

• Starting TCP Loops...

• Connection established with target Controller 1.

• Connection established with target Controller 2.

• Sending reset command to all targets...

• Preparing to deploy files to the targets...

• Starting download for target Controller 1...

• Opening FTP session to IP 10.10.10.4...

• Processing Action on Deploy VIs...

• Gathering target dependency files...

• Downloading 120 Dyno Controller.nivssdf [2226 kB] (file 1 of 6)

• Downloading 120 Dyno Controller_Controller 1.nivsdat [1558 kB] (file 2 of 6)

• Downloading PXIe-433x Timing Source.vi [25 kB] (file 3 of 6)

• Downloading Inertia RT Engine.llb [9257 kB] (file 4 of 6)

• Downloading Embedded Data Logger - Engine - PharLap.llb [1400 kB] (file 5 of 6)

• Downloading Pharlap System Monitor Engine.llb [331 kB] (file 6 of 6)

• Closing FTP session...

• Starting download for target Controller 2...

• Opening FTP session to IP 10.10.10.3...

• Processing Action on Deploy VIs...

• Gathering target dependency files...

• Downloading 120 Dyno Controller.nivssdf [2226 kB] (file 1 of 5)

• Downloading 120 Dyno Controller_Controller 2.nivsdat [1374 kB] (file 2 of 5)

• Downloading PXIe-433x Timing Source.vi [25 kB] (file 3 of 5)

• Downloading Embedded Data Logger - Engine - PharLap.llb [1400 kB] (file 4 of 5)

• Downloading Pharlap System Monitor Engine.llb [331 kB] (file 5 of 5)

• Closing FTP session...

• Files successfully deployed to the targets.

• Starting deployment group 1...

• Deployment group 1 is ready.

• Starting deployment group 2...

• Target Controller 1 is online.

• Deployment group 2 is ready.

• Preparing to synchronize with targets...

• Querying the active System Definition file from the targets...

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:

Error -307743 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

NI VeriStand:  The VeriStand Engine failed to start. A configured start trigger or external timing source did not occur within the specified timeout.

=========================

NI VeriStand:  NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> HP Loop.lvlib:HP Loop Main.vi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

• Unloading System Definition file...

• Connection with target Controller 1 has been lost.

• Connection with target Controller 2 has been lost.

[StephenB]

Great! That explains a lot. That box should not be checked since NI VeriStand wants to use that line on the backplane. Also, removing the other channels seemed to fix that deployment error as well.

The lines you need to connect between each controller are the lines you specified for the triggers. So PFIx on the DAQ card for Controller 1 and PFIx on the DAQ card for Controller 2. You also need to connect the BNC CLK IN to the CLK OUT of each chassis, as specified in the white paper.

[pmac]

With the trigger channels wired together the SDF now deploys successfully (thank you Stephen B), but it hasn't solved my original problem with reflective memory. Both "Ring Read Late" status channels indicate that the two controllers are not synchronized

To clarify my setup -

I have a PXIe-6341 Multifunction DAQ in slot10 of chassis 1 configured to export a start trigger on PFI0 and a PXIe-4300 Analog Input in slot 6 of chassis 2 configured to import a start trigger on PFI1.

PFI0 of chassis 1 slot 10 is wired to PFI1 of chassis 2 slot 6 (I don't think there's a problem here because it no longer times out waiting for the start trigger).

CLK10 OUT of chassis 1 is cabled to CLK10 IN of chassis 2.

Is there anything missing? Are there other things to try with regards to reflective memory?

Thanks

[StephenB]

Thats great (sort of).. at least your systems should be syncrhonized now.

Do the late counts go up gradualy or do they stay stable mostly and then sporatically increase by a whole lot?

Can you graph your HP loop duration channel and screenshot it here? Or even better log it, and all your late count channels and attach the log