error 1136 when adding FPGA in SysDef

[pmac]

I have a PXI-7854R Multifunction RIO installed in my PXIe-1075 chassis. When I add it to the System Definition file under the FPGA node, the RIO node is created with all it's subnodes -as expected- but the attached error dialog pops up. Everytime I highlight the newly created RIO node the same error pops up. Has anybody seen this?

I have a PXIe-6341 Multifunction DAQ designated as the Master Hardware Synch Device on Bus 2 and have routed PXI_Trig0 across all three buses.

Also, I'm using Veristand 2011 SP1.

Thanks

[StephenB · Accepted solution]

yes we have seen that. Thankfully it's just cosmetic. It happens when you have a DAQ master which is hidden in the tree and you click on FPGA devices. We hope to fix this in 2012. Sorry for the inconvenience

[Brzeski]

Hello Steven,

We've run into this error now with VeriStand 2012 where it was not an issue with VeriStand 2011 (or 2011 SP1) for us. If it helps troubleshooting, we are using a VS'11 project in VS'12. Any thoughts?

Thanks.

[StephenB]

We did not have time to fix this error in 2012, however the error is purely cosmetic and there is nothing bad about seeing the error other than the annoyance 😉

[vquemener]

There is still the bug in Veristand 2015!

[JiPé]

Hi guys,

vquemenere and myself we did encounter this behavior yesterday while adding an FPGA personality into our Veristand project.

We could reproduce repeatedly this behavior; and we found that, astonishingly, by expanding the DAQ part of the tree (every branches to the maximum), we did not get the error...

My guess is that the tree object is having issues at some point with a property node and this error appears for a local non-blocking problem.

As Veristand is codded with LabVIEW, would it be possible to just erase this specific error after a FPGA personality is called into the Veristand project ?

I guess it's too late to include this fix in Veristand 2015 SP1, but maybe for the 2016 version?

Keep the good work!

Regards,

[Roohcifer]

Hi all,

To reiterate what Stephen said, this is a known cosmetic issue (bug ID 376855 in case you want to track it on future VeriStand reame Bug Fix lists).  The issue occurs when clicking on an FPGA target in your system definition when your master DAQ timing device (highlighted in blue) is not opened in your system definition tree.  If it is an annoyance, you can open your system definition and go to Tools>>Options>>System Explorer Environment and set the Maximum automatic expansion level to 6.  This will open your system definition tree every time you launch it from then on down to the DAQ device level, which will ensure that your master DAQ timing device has been exposed before you click on your FPGA device.  That said, it's a totally cosmetic error that does not affect the behavior of your system definition. 

Happy real-time testing 😄

Regards,

[JiPé]

Hi Roohcifer,

Thanks for the workaround and the Bug ID.

Have a great day.

[ZX81]

I'm using VeriStand 2018.  I'm getting error 1136, and it does NOT appear to be simply cosmetic.  I eventually got it working, but not easily.  It all centered around having a screen reference a deleted tag.

I created a custom FPGA program.  It was working fine.  Then I noticed I had a typo in the tag names, so edited the XML to fix it.  Now, I get Erorr 1136.  The nivsscreen editor lists some of the corrected tag names, and some of the old names. 

I tried deleting the FPGA entirely.  Some tags still showed up in nivsscreen editor (mostly wrong ones that I had deleted), most did't.

I went through my screens (only 1 in my sandbox for now), and changed every control/indicator that referenced the wrong FPGA tags to a different tag.  That didn't help, with or without the FPGA configured.

So I loaded a sample FPGA program that ships with VeriStand examples.  It looked good in the System Definition (but had error 1136 still).  In nivsscreen editor, none of the example's tags showed up, and I still had some of the typo tags from the other FPGA configuration.  I deleted the FPGA again, and even quit veristand entirely, and came back.  Then, the example's tags showed up in nivsscreen (even though it was deleted).

Eventually, I deleted all FPGA references (including ones that weren't wrong), and deleted & recreated the FPGA a couple times, and it came back, without an error message.