06-02-2015 08:30 AM
Our setup is running VeriStand on a cRIO 9081 chassis using an FPGA personality. We were looking at adding a 9144 ethercat expasion chassis to the system. Does VeriStand support runing the cRIO chassis and expasion chassis in FPGA personality mode? I can't seem to find much information on that, other than runing the system using the scan engine.
We initially tried to run our system uisng the scan engine add on, but the system had issues with the NI 9213 16 Ch thermocouple card. If one of the inputs is open it would read the rest of the channels as open. For example if channel 5 is open, then the remainging channels 6 through 16 would also read as on open. Due to this reason we setup a FPGA personality to read the I/O.
Thanks
Solved! Go to Solution.
06-02-2015 08:49 AM
You can do it. But you need to compile FPGA in a hybrid mode:
http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690
CLA, CTA, CLED
07-02-2015 08:13 AM
i'm not sure if this is the same solution that you mentioned, but I created a bit file for the modules on the main cRIO chassis and then added the EtherCAT chassis as scan engine custom device. I took a screen shot of my project in VeriStand.
is the solution that you mentioned differrent then the one that was implemented in the attached pictures?
07-03-2015 01:15 AM
It is not clear, if you would like to program FPGA on cRIO or on 9144. It is possible both.
What you did is FPGA on cRIO.
To program FPGA on 9144 if needed, you need to add compiled bitfile to EtherCAT chassis under Scan Engine CD section....
CLA, CTA, CLED
07-06-2015 09:11 AM
Thanks for the reply. Adding the EtherCAT chassis in FPGA mode would be the preferred method. I wasn't aware that this could be done. After doing some research, I was able to setup the two chassis (primary 9081 and secondary EtherCAT 9144) in FPGA mode. Attached is a picture of the project setup.
I'm guessing that the next step is to setup the bitfile for the EtherCAT secondary chassis in a similar method as settting up the pirmary chassis (bitfile and XML config file)? I wasn't able to find documentation that would indicate that this process would be different.
07-07-2015 05:56 PM
Hi Emmett,
The process is certainly the same for adding a second 9144 slave chassis. So you will compile the FPGA VI in the LabVIEW project and add the bitfile in VeriStand under the "User Variables" category in the Scan Engine EtherCAT custom device.
Cheers!