NI VeriStand

[BSI]

Part 2 of 2:

To recap:

- VIs from part 1 and DeltaloopTime.vi are used by the model vi.

- the Test RT GenVolt Updates - SW Timed.vi used the model vi with RT to test it.

In RT,  it works fine, when you increase the timed loop iteration rate > 1kHz, the digitization of the procuded sine is at the correct rate.

In VS, the digitization appears fine as per the small spikes I can see on the scope at the right rate, however the sine values only updates at 1kHz, no faster even when PCL is set > 1kHz.

L.

[Devin_K · Accepted solution]

Hi Laurent,

I figured out what was wrong with your model.  The short answer is that you need to remove the conditional disable structure from DeltaLoopTime.vi (getting rid of the Windows case). 

The way it is currently compiling, it is using the ms Tick Count in the Windows case for the timing.  Because of this, your timing resolution in the model is only 1ms, so you only see the sine value change every 1ms.

What's happening is that when you build your VI into an lvmodel, a projected is scripted behind-the-scenes.  Your model VI is put into a template in this project under and built into a .dll.  Because this build is located underneath the "My Computer" target in the tempory scripted project, the wrong case is being used in the DLL.  Unfortunately, since all of this scripting is done behind the scenes, there's no way you can force it to compile correctly.

So, in order to force it to compile with the us Tick Count, you need to get rid of the conditional structure.  I compiled and tested this in VeriStand and the model now updates at the correct rate.

Devin

[BSI]

Devin, you are right !  It works here as well, at the expected digitizing rate.

Thx.

Laurent