Why system defination fails for timeout error?

[Nil@Lear]

Hello,

I have modified FPGA personality code for frequency measurement of PWM inputs.

After that I have generated bitfile successfully but when I try to deploy it fails for “Error -307276: one or more targets failed to start within the specified timeout. Verify that any start trigger or clock signal are configured correctly”

This was deploying and running properly before modifications.

Please let me know the reason behind this common error or any errors in coding.

Urgent help will be appreciated.

I have attached error and FPGA personality code screenshots.

Thanks and Regards,

Nilesh

[pmac]

I was getting that same error and all I had to do to be able to deploy my SDF was increase the timeout specification in the project file properties.

In Project Explorer right click the project name and select Properties. In the dialog that pops up select Veristand Gateway. In the Veristand Gateway settings you can specify an amount of time to wait (Default = 120000 ms), or you can set it to wait indefinitely.

For me, this didn't resolve the increased deployment time but it kept me up and running until I figured it out.

PatM