04-15-2013 10:37 AM
So I can't seem to figure out why this is happening...
If I deply the VS project to the RT target with both FPGA's enabled (RIO0 and RIO1), it fails to deploy everytime. If I disable RIO0 and enable RIO1 - it works. And same goes the other way around (enable RIO0 and disable RIO1) so I know that my FPGA code and *.fpgaconfig file work correctly.
Anyone know why this would be happening? I did a couple searches but didn't come up with anything.
Thanks in advance for the help.
Solved! Go to Solution.
04-15-2013 12:25 PM
What is failing? Do you see any specific errors reported?
04-15-2013 12:52 PM
huge shot in the dark here....
Guessing you have an 18 slot chassis, you're using NIVS 2011 SP1 or earlier, and the cards are in different bus segments of your chassis (aka, pretty far apart)?
If so you need to go into MAX, select the controller -> hardware -> chassis -> triggers (bottom tab)... and route trigger line 0 away from the RIO device that is bold blue in your system definition (which is the master device specified on the chassis page)
If I get this with no error information at all and a total guess I think I deserve a kudos. Otherwise nevermind 🙂
04-15-2013 01:23 PM
Nice shot. Seems to be working just fine now. If it wasn't your job I'd say you spend too much time in VeriStand, haha.
04-15-2013 01:41 PM
yesssssssss!
haha
04-15-2013 01:42 PM
just fyi NI VeriStand 2012 will do this automatically for you now. when/if you upgrade make sure to revert MAX to "dynamic" routing mode. the upgrade notes in the readme of 2012 says this
04-15-2013 01:56 PM
As I was going in there and changing I thought I recalled hearing that 2012 fixed this problem, but I had never run into it before so it never hit me to check it out at all. In fact when I heard about it I probably just was like "Oh that's never happened to me" and then proceeded to think about something else. Oops... lol.
Thanks for the help though.