VeriStand FPGA Personality Is Late? and Handling Latent FPGA Data

[Pie566942.0]

I'm using a 7853 FPGA (only) in a PXIe 1071 chassis with an 8135 controller and running VeriStand 2013 SP1.  At the end of my test, I want to guarantee the integrity of the test, which includes verifying the FPGA interface was never late.

Initially I thought to expose the "Is Late?" terminal as a channel, but then I noticed it's not really a count, it's just a flag.  Furthermore, it seems that flag is not latched, it only signals per interface loop iteration.  This makes me think VeriStand's FPGA interface design intends that I trigger a VeriStand alarm on the Is Late? channel.  Am I correct, and if not, how does NI intend I use the Is Late? terminal?

Since the DMA nodes in the FPGA never time out, there's no sense looking at the Timed Out? terminals on the FPGA.  But, the effect of a timeout would appear in the Is Late? terminal.  I'm tempted to change the Is Late? U64 into an actual count of the number of Is Late? flags set by synchronize to host VI.  Is there any reason not to do this?

How does VeriStand handle a late FPGA?  If the RT-side of the DMA buffer was getting increasingly full, the data from the FPGA would be increasingly latent, which could lead to instability in the system.  I'm hoping the VeriStand engine would purge the data latency, but I see nothing in the FPGA interface that would facilitate this.

Thanks for your help,

Steve K

[StephenB · Accepted solution]

Hey Steve,

If the NIVS PCL reads that flag as true, it incrememnts the HP Count system channel.

For the FIFO depth question: The PCL always expects to read and write a fixed # of packets every iteration (as defined by the XML), and FPGA always reads and writes the same # of packets each comm loop iteartion, and since the timeout is set to -1... a backlog can't be accumulated. The packets act as a hand shake.

[Pie566942.0]

Thanks Stephen.

On the second note, wouldn't this require some kind of timing synchronization between the host and the FPGA?  From what I see, the FPGA loop is timed with a Loop Timer node, and I only have the option for "Automatic Timing" on the controller.  If the RT clock is a little slower than the FPGA clock, couldn't the FPGA write into DMA more often than the host reads out?  I see an interrupt in the Synchronize to Host module.  How is that used?  I'm sorry if I'm missing something in the documentation.

Best,

Steve K

[StephenB]

No worries. Great question. And we don't document any of this stuff so understandable.

Yes the FPGA, if it is the master, times itself with a loop timer and clocks other devices inside the PXI chassis with a pulse generated on the PXI_Trig0 line. That loop also toggles a boolean variable that is used to clock the DMA loop. The DMA loop fires an interrupt every iteration, which the host waits for. So the hardware does the timing of both itself and the PCL via the interrupt. When the PCL is set to automatic timing, it will look at your hardware and pick the device to time the PCL... in this case... the FPGA interrupt

[Pie566942.0]

Thank you Sir!  I should not keep track of the number of Is Late? flags in packet 0 because they roll up into the HP Count.

I think a good place for that note would be in this document: Creating a Custom FPGA Configuration File.  It already contains this text, "You might want to use an empty packet for the first DMA_Read packet because the first bit of the first DMA_Read packet always contains a Late Status field by default. If you specify an empty packet for the first DMA_Read packet, this unusable Late Status bit does not appear in the System Explorer window configuration tree. If you want the Late Status bit to be visible in the System Explorer window configuration tree, you can specify it as a Boolean channel in the first DMA_Read packet."

The timing details, IMHO, would be nice in the Understanding the VeriStand Engine topic.

I know you're all very busy.  I appreciate your support!

-Steve K