VeriStand DAQ and FPGA timing and synchronization questions.

[Krid]

Hello,

I’m currently experimenting with increasing the PCL loop rate of our VeriStand systems. We normally use 1KHz for our productive systems but we have the desire to increase the frequency. I created a test-system definition that only includes our DAQ cards and our FPGA card. The problem I’m facing is that the system definition does not deploy when the FPGA card is configured as the chassis timing master.

I’m getting the following error:

Details:

Error -200714 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

Acquisition has stopped because the driver could not transfer the data from the device to the computer memory fast enough. This was caused by computer system limitations.

Reduce your sample clock rate, the number of channels in the task, or the number of programs your computer is executing concurrently.

=========================

NI VeriStand:  HP Loop.lvlib:HP Loop Main.vi<append>

Task Name: PXI1Slot10_AI

When I use one of the DAQ cards as chassis master, the system definition deploys fine.

The hardware components used are as follows:

PXIe-1085 chassis with the following IO cards:

• Slot2: NI PXI-6723
• Slot3: PXI-7841R
• Slot5: PXIe-6363
• Slot8: PXI-6528
• Slot10: PXIe-6363
• There are also additional cards in the chassis but these are not used for the experiments I’m currently doing.

We use VeriStand 2015 SP1.

Can somebody please explain why it makes a difference whether you choose the FPGA card or a DAQ card as master?

On productive systems we use Waveform acquisition on the analog inputs of the PXIe-6363 card in Slot 10. So when I change the sampling mode from single point to waveform acquisition on the card in the experimental system definition, it deploys fine with the FPGA card as master. Does that make any sense?

I have read in this whitepaper
http://www.ni.com/white-paper/14637/en/

that you should turn on the PXI Chassis Clock Synchronization on the FPGA device. Is this correct? I have done that but didn’t notice any difference (it still fails to deploy with FPGA as master).

Also, what exactly does the “PXI Backplane Reference Clock” do on the DAQ cards? My understanding was that the sample clock of a (non-master) DAQ card is derived from the sample clock of the chassis master device. Is the 100MHz or 10MHz used in addition to the master clock? If yes, for what purpose? Which clock is chosen when the setting is “Automatic”?

Regards

Dirk

[timtamslam]

When you have FPGA as master, do you still get the deployment error at slower PCL speeds?

You might find this discussion interesting: 

https://forums.ni.com/t5/NI-VeriStand/Why-is-DAQ-200714-error-fatal/td-p/3276882

I can't answer whether or not the reference clock is chosen in addition to the master timing clock but your question about what is chosen with Automatic is covered in the help. Basically it comes down to chassis type. PXI = 10kHz, PXIe = 100kHz. 

http://zone.ni.com/reference/en-XX/help/372846H-01/veristand/cp_daq/

Section: PXI Backplane Reference Clock

[Krid]

Hello Tim,

when I select a DAQ card as chassis master my experimental system definition deploys at 5000Hz PCL rate. 

When I change the chassis master to the FPGA card, the situation is as follows:

5000Hz -> fails to deploy

500Hz -> fails to deploy

100Hz -> deploys successfully

I didn't try to find out at which rate exactly it fails to deploy but obviously the difference in maximum achievable clock rate is huge. I would like to understand why there is a difference.

Thanks

Dirk

[timtamslam]

That's a much larger drop than I would have expected. I'm not sure what's happening and we'll likely need help from someone at NI to troubleshoot further.