PWM generation using counter within Veristand

[Ryan_S]

Hey Rajamodol,

I just set this up and it worked without error, using a PXI-6602 and 8 counters; I've attached the project and other files. I tried to mimic your setup as best as possible, including placing the card in Slot 3, so you should only need to do the following to test my project with your system:

1. Open the Project

2. Open the System Definition File

3. Change the IP Address of the controller to be that of your PXI

4. Deploy and test changing the Duty Cycle and Frequency from the controls I have on the workspace

If this does not work, please also reply back with your project so that we can take a look at it. Also, you mention that the error occurs when you modify the frequency. What are you changing the frequency to? If you set it to 1100, 1200, 1300 Hz do you get any errors? 

--Ryan_S

[rajamodol]

Hi Ryan_S,

Thank you for your example. I have tried it and realized that the errors were generated if i set the frequency input too low, let say 1 Hz. But i need to do it, it will simulate PWM at very low frequency.

I have created a custom device which is working perfectly at low frequency input. I inserted the following configuration in my Custom Device RT-Driver VI.

My question is: How can i get property node CO.RdyForNewVal  without custom device? I would like to use native DAQ-driver from NI Veristand.

Thank you again,

Rajamodol

[Ryan_S]

Hey rajamodol,

I was able to reproduce this behavior and it has been documented as a bug in CAR# 422293. The error you're seeing is caused by VeriStand trying to reconfigure the counter before its ready to receive a new value. By using the case structure and CO.RdyForNewVal property you prevent VeriStand from configuring the hardware before its ready to accept new values, which should be after 1 iteration at the current value (as stated in the error). However, this simply means that the Custom Device is delaying the setting of this value behind the scenes. The same outcome can be achieved with the built in DAQ functionality in VeriStand by waiting X amount of time between changing the frequency, where X is based on the frequency you're changing from. So, if your frequency is currently set to 0.5 Hz, it's going to cycle every 2 seconds, which means you'd need to wait about 2 seconds from the time you set it to 0.5 Hz to when you change the frequency once again. This delay period may not be exact, but you should be able to benchmark it pretty easily with your custom device by seeing how long after receiving a new value it takes before you get into the true case of the case structure. Then, in your Real-Time sequence or TestStand, you would simply run code to ensure that you wait the required amount of time before modifying the counter frequency.

--Ryan_S