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PCL rate jitter on PXI realtime targets

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Hi,

 

I would like to get some feedback or opinions about what jitter-values are to be expected on a RT PXI system running VeriStand.

 

We usually run our system definitions with 1000Hz PCL rate. The "Actual Loop Rate" system channel usually "wobbles" between 995 and 1005Hz. This is what I would consider "normal". However, occasionally (every 10s or so), there is a loop that has a considerably larger deviation like 950Hz or 1050Hz.These +-50Hz are a larger deviation than I would expect for an RT system. I don't know why this amount of jitter occurs. It even happens without any custom devices in the system definition so I don't think that it's a user fault.

 

When I increase the PCL rate to 5000Hz, the jitter is usually +-200Hz which I think is way too much. It doesn’t matter if I choose an FPGA card or DAQ card as chassis timing master.

 

What are your experiences with PCL rate jitter on VeriStand?

 

Thanks
Dirk

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Hi,

 

The rate of the jitter depends on the software configuration you have. If you refer to the attached document, it outline techniques for improving the VeriStand execution speed. The document is intended as a guideline. 

 

I hope you found this useful.

 

Many thanks,

Harith Rothi

 

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Hello Harith,

 

thanks for your answer. I have a question regarding the document you attached: How did you measure the jitter on your system?

 

I'm starting to believe that only the calculation for the "Actual Loop Rate" system channel is poorly implemented and the actual jitter is much better than indicated by the channel.

 

When I trigger a transmission of a CAN-Message via a realtime sequence and analyze the bus with an external monitor, the message-delta times are very consistent and I don't see any relevant jitter. I also created a rectangle signal (toggled a pin) from a realtime sequence and measured the pulse width with an oscilloscope. I have some resolution issues with the scope but as far as I can tell the jitter is below 1%, i.e. much better than indicated by the system channel. 

 

It certainly is a relief that the actual jitter seems to be quite good but the question remains why the “Actual Loop Rate” channel displays bogus values.

 

Regards
Dirk

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It is important to know that what matters is timing on HW io. It is driven by HW clock and f.e. could be synchronized on PXI between multiple boards. So if you feed data even with some jitter (f.e. because of handling interrupts) early enough to driver and read on time,  the jitter from PCL SW part doesn't matter because IO s will be timed by HW clock...

CLA, CTA, CLED

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Jiri,

 

I agree that the timing of the hardware IOs is what matters and the measurements I made with external devices seem to prove that the HW timing is quite accurate.

 

Since the PCL is timed by HW clock (of the master DAQ card / FPGA card, correct?), I didn't understand why the "Actual Loop Rate" channel has so much jitter. Because there is no way that the HW oscillator could be that bad. Now I think what happens is this: The start of a new PCL iteration is triggered by the HW clock, however, before the execution flow reaches the piece of code that calculates the "Actual Loop Rate", interrupts occur or don't occur, or context switches occur or don't occur. Therefore, the system channel has the jitter. But in the end this "software-jitter" doesn't really matter as long as all the code gets executed in the period that is given by the HW clock (I know this is basically what you said but it felt good to write it down myself Smiley Happy ).

 

Regards

Dirk

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Accepted by topic author Krid

Dirk,

 

exactly, 

Since the PCL is timed by HW clock (of the master DAQ card / FPGA card, correct?) - Depends on settings in System Definition. If it is DAQ, the blue device is master... For FPGA on PXI don't forget to set PLL to PXI 10 MHz clock in RIO Device settings. So FPGA doesn't drift from PXI clock.

 

If I remember properly, if FPGA is master, than PCL is triggered by interrupt set by FPGA. You can check in FPGA template subVIs...

PCL is timed loop (blue) in LV. So the PCL Actual Loop Rate is actually measured by timing engine of that LV timed loop (in SW).

 

Therefore, the system channel has the jitter. But in the end this "software-jitter" doesn't really matter as long as all the code gets executed in the period that is given by the HW clock and boards (clocks) are synchronized...

 

~Jiri

CLA, CTA, CLED

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