HP Loop duration increases with two FPGA on PXIe-1082, HP count increases

[Rokot]

Our system: PXIe-1082 Controller 8840 with 2 PXIe-7822R-FPGA
VeriStand 2016 with a target loop of 5kHz
FPGA code is custom with VeriStand FPGA interface http://forums.ni.com/t5/NI-Labs-Toolkits/NI-VeriStand-FPGA-Based-IO-Interface-Tools/ta-p/3493285 with an FPGA Clock of 40Mhz.
If only one FPGA is included in the project, everything works fine with a HP Loop Duration = 35us.
After adding the second FPGA, there are two options:
1) Turn on the sync RIO0 / RIO1 (no matter), the HP duration has only increased by 15us, but the HP count quickly increases. Why?
2) Set synchronization to "none". Then it behaves well at the beginning, but the HP Loop Duration rises slowly and starting from about 170us the HP count rises. Then the HP Loop Duation is again at 50us and rises again.
So I not completely understand the sync. Each FPGA clocks itself with 40Mhz and pushes over values ​​in / from the DMA. Why does the HP Loop Duration increase to read / write the values? 40MHz more or less are only 25ns.
The description http://www.ni.com/white-paper/14637/en/#3.HardwareTimedSinglePointDAQandFPGAviaMXIeRIO doesn't help me, because we have an R series that provides synchronization.

[Rokot]

No I set the Loop Rae at 50Hz, but in sync mode the HP count still increases, although the HP Loop Duration with 60us is sufficient for 50Hz ... I dont get it.

[HoussamK]

Hi,

you wrot "If only one FPGA is included in the project, everything works fine with a HP Loop Duration = 35us."

Are you sure you are seeing 35 us HP Loop Duration?

[Rokot]

Yes, without modell and with parallel mode: Target Rate=5kHz, HP Loop Duration=20us with 1. FPGA at RIO0

Add second FPGA at RIO1 with synchronization of chassis on RIO0: HP Count increases, HP Loop Duration constant at 35us SDF of VS-Project:

With none master sync get this: HP Loop increases from 35us to 170us -> HP Count goes up, HP Loop Duration starts at 35us and so on:

->

Now I see that the Last Late Iteration=-1 always?

[HoussamK]

Could you run your system with the PXI bitfiles that ship with VeriStand 2016 ( Users\Public\Documents\National Instruments\NI VeriStand 2016\FPGA), do you have 2 suitable FPGA Modules for this particular test situation?

[Rokot]

We have only three PXIe-7822 FPGAs. But I will build a bitfile for the 7822 from the 7831-project (C:\Users\Public\Documents\National Instruments\NI VeriStand 2016\FPGA\Templates) an run it.

[HoussamK]

I suggest the NI VeriStand Add-On: FPGA XML Builder Node

The VeriStand FPGA XML Builder add-on allows users to simplify FPGA VIs being developed for use with NI VeriStand.

More info : NI VeriStand Add-On: FPGA XML Builder Node

[Rokot]

The problem with this node is that we have measured one iteration (of 5kHz) delay at the values that are passed into the FPGA. With the standard procedure, we have not seen this delay. So we have already 2 project running. But as we move more into the FPGA calculation, we need two or more FPGAs in the system. Each one works for itself, only together does this behavior.

[Rokot]

Now I builded the NI VeriStand FPGA IO PXI-7831R.lvproj for 7822 and changed only the bitfilename for the 7822 in the xml-file. an can run it not with one FPGA with Loop Duration of 13us and 2 FPGA an sync mode RIO0 with a Duration of 24us with a Target Rate of 5kHz.

But I dont undestand why I cant do it with my FPGA...

ok now I need to increase the FPGA slowly with new logicand DMA-Variables and test it.

[HoussamK]

.. and why do you not follow the instructios described in NI VeriStand FPGA-Based I/O Interface Tools ?

The NI VeriStand Custom FPGA Project Wizard guides one through the process of selecting your FPGA...