HP Loop duration always increases with 2 FPGA on cRIO 9082RT

[StephenB]

also, in your "Clock_read.PNG" you have the right side of the VI showing reading the voltage... that is wrong. it should set the voltage on the left side (like you are) and do nothing in the right side.

See:

Change that and use FXP constants instead of integers and it should work

[R.Kaszubiak]

Hi,

I have already tried to replace cast by constant but it has no effects.

And I think I am obvious put the right side of my "READ_CLOCK.png" to detect the lower edge of the clock.

If I don't put this part, it could be believe detecting a second rising edge while it the same high level of the clock because of the loop is executing faster.

I have developped the same software code but with a 9222 module (AI) which is faster than the 9205 and my actual loop rate varies between 990Hz and 1022Khz and it is due to the clock generation frequency which varies between 990Hz and 1022Khz too.

Reminder : With the 9205, the acual loop rate varies between 860 and 1200Khz.

R. Kaszubiak

[StephenB]

ah good point. I forgot about that part