08-08-2012 09:17 AM
Do you put the "Host" vi in Teststand as say a Numeric Limit tests? Does the host load the FPGA VI everytime its called in TS?? Does the FPGA VI have to compile each time so that the user has to wait??
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08-08-2012 10:11 AM
The way I did it was I had a VI to talk to the FPGA card. This VI was ran in a new thread (you may have to put it in its own sequence to do this). I then used queues to send commands to the interface VI and back. So a test step would send a command to the FPGA via the queue, recieve data back via a second queue, and then return the data to TestStand for limit checks.
08-08-2012 10:55 AM
From what I found out about Labview and FPGA ( assume you have all the required FPGA components) is that you create a Project , create a Host Vi then a FPGA VI. The FPGA is complied when you hit the run button and auto downloads onto the FPGA. You communicate w the FPGA via the Host.vi. I have gotten expierence w Run VI Asynchronously so I assume you would run the Host vi in this thread using Run VI Asynchronously. After that you lost me w the queueing. Are there any examples of how to do that? Do you have to use queues because the vi is still running when you pass it parameters?? My question still is when you run the Host vi in Teststand does the FPGA VI compile EVERY TIME?? This, in my case, takes over 10 mins.
08-08-2012 11:13 AM
You should compile the FPGA into a bit file. You can then load the bit file in the host VI. This loading should only happen when the host VI is ran.
10 minutes to compile? That is quick!!! I had one that took 2 hours and I've heard stories of some taking a lot longer.
The Producer/Consumer architecture is the closest thing I can compare my setup to. Yes, I use the queues because the host VI is constantly running. You have to use some kind of messaging in order to pass data into the host VI. I used an Action Engine to keep my queues in order, but you could probably just use named queues to accomplish the same task.