Hi, I'm trying to demod a simple QPSK test signal (12Kbps data rate, 70MHz, 24 bit repeating data sequence). I used the DQPSK example project included in the library and blindly replaced the DQPSK demod (FPGA) .vi with the QPSK demod (FPGA) vi. I believe I've got my filter coefficients set correctly and the decimation/symbol rate/ADC Clock Rate correct, but my data is not demoding correctly. Have I taken too much of a shortcut in black-box replacing the DQPSK and QPSK vi's? Also, in traditional LabView QPSK demods, I've had to run through about 15 combinations of inverting the demoded bits depending on whether the demod locks to the I channel or the Q channel first. Is this something I'll have to do with the FPGA version as well?
If there's a regular QPSK FPGA demod project available, that would be fantastic.
Thanks a lot.
The decoder has a few constant multipliers which are dependent on the generator polynomial. It might be difficult to change those manually. We are working on simplifying it. When would you need this block? Can you please share the details of this project?
i have been working with viterbi encoding/decoding example given in Rf communication library for FPGA's . As per specifications is a 1/2 decoder with constrain length 7. Can I modify it for other decoders e.g. 2/3, 5/6 etc
1- Actually I am interested in decoding part only. I already have a 2/3 or 5/6 encoded file. But I am confused how to tell the viterbi decoder vi that given input is a 2/3 or 5/6 encoded . As u See usually we need a generator matrix for decoding (and encoding as well). But here the vi for viterbi decoding residing in FPGA vi is not having such generator matrix as input it only has a trellis information input.
2- How does a trellis information specify the encoder type (ie either it is 1/2, 3/2 or 5/6). I am not getting it.
3- How should I modify the trellis information vi for my 2/3 or 5/6 decoder Also the given example has a sub vi
calculating trellis info which takes 1D array input. And for 2/3 and 5/6 I have to have more than 2D array isnt it so.
The Viterbi decoder and the trellis info vi on NI-Labs was designed to handle code rate=1/2, constraint length=7 and without puncturing. If you have Modulation Toolkit installed, you might want to look at the algorithm being used a generic use case and then modify the fpga code.
Tnx for the reply . I have been looking into the modulation toolkit convolution decoder. Where I find decoders fore different rates and different Generator Matrix. AS u see in these decoder for every rate there is Generator matrix being calculated or for every Generator matrix there is a code rate respectively. And these generator matrices are multidimensional ones. As per specification FPGA Vi's cannot support multidimensional array. Will u plz suggest some over view for recoding for different rates what should I pass from Host vi to FPGA vi and what should I be doing in FPGA Vi. Is there any way to pass Multidimensional array to FPGA Vi. Keeping in mind that I want more work to be done by FPGA Vi rather than Host VI.
If anyone familiar with viterbi decoding IP in Labview FPGA reading this can i amend my 1/2 viterbi decoder to 2/3 or 3/4 decoder using puncturing .... If not why not? If yes then How?