09-18-2009 11:55 AM
I think I know where the confusion is. NiFpga_ConfigureFifo only configures the host memory side of the FIFO. But the FIFO on the FPGA holds elements as well. So the total number of elements your FIFO can hold is essentially the sum of the host memory side and the FPGA side. The size of the FIFO in the FPGA is configurable from the LabVIEW Project, and defaults to 1029. Does this make more sense?
09-21-2009 07:29 AM
Yes I was confuse but still I don't understand what is this for?
I've cheched NI-RIO FIFO example and there isn't any FPGA_ConfigureFifo function? Is this function needed??
My DMA Fifo is configured in my LabVIEW project (4095 U8). Then I compile FPGA VI and then generate C API files (LVbitx).
Is this enough to work properly Or do I need to configure something in C application?
When I use an FPGA card using LabVIEW I don't need to configure a FIFO DMA in the host! Or maybe it's automatic?
09-21-2009 11:18 AM
This function is optional, which is why you don't see it used in the example. Please see my reply on 9-11-2009 for more documentation on this function.
09-22-2009 03:11 AM
Ok for this point.
Can you explain this :
I've configure a DMA FIFO with 255 U8. In My FPGA I placed the function : Get Number of Elements to Write.
I run the code in simulation mode and it returns 10255?
Any explaination? Shouldn't it be 255? and 254 after I put one element in the FIFO and so on?
09-22-2009 11:31 AM
That actually makes sense, as the minimum size is 10000, and it looks like the numbers were just added together.
These questions are actually not specific to the C API, but the FPGA Interface in general. I suggest you try the general LabVIEW FPGA forum: http://forums.ni.com/ni/
09-24-2009 05:35 PM
I am trying to read a FIFO and am getting a status error of -50400. Any idea what this is?
I can verify the status error -63101 by misplacing the bit file, so I'm pretty sure the error is correctly displaying.
09-24-2009 06:10 PM
Yes, that is an error code that we forgot to document! It's the error you get when a FIFO operation times out. This happens when you specify a finite timeout and the operation does not complete in time. We will be documenting this error in the next release. Sorry about the confusion.
09-29-2009 03:26 PM
I found another one...
-52012. The error explanation (Help>>>Explain Error) says "There is no more data available to read or no more space available in which to write." This is pretty vague...
Since I'm playing with IRQ's now, I'm assuming it's an IRQ issue.
09-29-2009 04:54 PM
I think I found the problem. It looks to me like you may be calling NiFpga_WaitOnIrqs on an NiFpga_IrqContext that was never reserved with NiFpga_ReserveIrqContext. In future releases, this will probably return a more descriptive error like NiFpga_Status_ResourceNotInitialized.
Let me know if this isn't what's happening, and thanks for the feedback!