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C Interface to LabVIEW FPGA

harBenger,

 

With released 1.0 version announced above, you will find examples not only of how to use different features such as FIFOs and interrupts, but also example .sln and .vcproj files for using the C API with different versions of Microsoft Visual Studio.

 

The C API was actually created to be extremely cross-platform, so it should integrate well in whichever environment you end up using.

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Message 51 of 79
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thanks kentyman,

 

I was more interested in developing in .NET languages (VB.NET or C#). I want to find the simplest way of accessing the FPGA in VB.NET.

 

From my initial research, it looks like I will have to develop my own C++ DLL wrapper which calls .h, .c, and .dll files and can be called from VB.NET. Am I missing something?

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Message 52 of 79
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harBenger wrote:

thanks kentyman,

 

I was more interested in developing in .NET languages (VB.NET or C#). I want to find the simplest way of accessing the FPGA in VB.NET.

 

From my initial research, it looks like I will have to develop my own C++ DLL wrapper which calls .h, .c, and .dll files and can be called from VB.NET. Am I missing something?


harBenger,

 

Now I see what you mean. You may wish to use C++/CLI (or the older Managed Extensions for C++), which is itself a .NET language that supports a C/C++ syntax. However, if you want to use VB.NET, then I think the option you mentioned may be your best bet.

 

Incidentally, we chose C because of its interoperability with so many other languages so you could do this very thing.

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Message 53 of 79
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Hi

 

When I use FGPA interface C API there is a function available named configure FIFO.

 

Can you explain what is it for? I thought it was impossible to dynamically configure DMA FIFO? Am I wrtong? 

 

Thanks a lot.

 

 

James

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Message 54 of 79
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julesjay,

 

 

The documentation for NiFpga_ConfigureFifo in NiFpga.h states:

 

/**
 * Specifies the depth of the host memory part of the DMA FIFO. This method is
 * optional.
 *
 * @param session handle to a currently open session
 * @param fifo the FIFO to configure
 * @param depth the number of elements in the host memory part of the DMA FIFO
 * @return result of the call
 */

 

While you can't change the FIFO depth on the FPGA, you can change how many elements are available in memory for your host application. This is, however, optional.

 

It basically accomplishes the same thing as the FIFO.Configure method of the LabVIEW FPGA Interface. You can also read more about it by reading the "FIFO.Configure (Invoke Method)" topic in the LabVIEW Help.

 

Hope this helps.

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Message 55 of 79
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I think I've found a bug in french version into the lvbitx file in the Numeric type see extract from lvbitx :

 

<Type><U8>
 <Name>Num&#233;rique</Name>

 </U8></Type>

 

I don't know if it's a know issue but ....

 

 

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Message 56 of 79
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Thanks for your answer about DMA FIFO. 

 

 

I've got a problem using it with C interface. 

 

I fill a DMA FIFO into the FPGA.  I read it in my C application and I'm to slow to read it before it's full.

 

My problem is that when it's full its seems to crash the FPGA.. If I stop filling it and continu reading it , it will never be empty.

 I've tried to set timeout to -1 and 0 => same behaviour. 

 

Is it normal? I thought that when a DMA FIFO is full, the full flag became true and I just lost the first element in it

 

Have you tried this case ??

Maybe I don't understand how to use it? 

 

 

James

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Message 57 of 79
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James,

 

The error with escaped characters in the bitfile is a known bug that we're working to fix. Thanks for reporting it!

 

As for your problems with FIFOs, I'm not exactly clear on what you're doing. In particular, I don't know what you mean by "crash the FPGA". You're saying that if you put a finite number of elements into a Target-to-Host FIFO, you can read an infinite number of elements out? What sorts of numbers of elements are you talking about? If you put one element into it, you can you read two out?

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Message 58 of 79
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By crash the FPGA, I mean "freeze" : nothing appends after....

 

I've configure a DMA FIFO with 4096 U8.

 

On FPGA side, I write data into FIFO and I read these data in my C application. An indicator allow me to know the amount of data available into the DMA. I've tested it and the behaviour seems correct. 

 

But at this time I'm to slow to read these data as fast as they are written. So the amount of data available in the DMA reaches 4095 U8.

At this time the FIFO full output should goes to true. it's not.

The data I add should be lost for 0 as timeout value, the fifo should wait for -1 as timeout value. 

 

In my case i've tested to go to 4095 U8 then after a short time, I stopped adding data into FIFO and continued to read these data in C application. Logically, after a time the amount of data should decrease but it never !!! 

 

It's like my FPGA freeze and I need to restart it. 

 

 

I hope i'm more clear... 

 

 

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Message 59 of 79
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Hi,

 

I've updated RIO 3.2 to RIO 3.2.1 and I've made some changes.

 

It doesn't freeze anymore.

 

But I still don"t understand the FIFO behaviour....I'll make some test this afternoon (here) to ry to understand. 

 

James

 

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Message 60 of 79
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