NI FlexRIO Development Tools Discussion

[viScience]

Can any of the concepts or code from the toolkit be used with the cRIO?

[dklipec]

With the exception of Adapter Module specific code (such as NI 5761 Channel...), or code that specifically requires DRAM, all the code should run on any target supported by LabVIEW FPGA.

[viScience]

Is the DRAM essential for the transfer of waveform data back to the host?

[dklipec]

In short, no.  Most of the example instrument driver FPGA personalities can be reconfigured to use Block RAM by changing the selection on the Polymorphic VI that currently uses the DRAM memories.  It has options for storing to Block RAM (BRAM) instead.  We do not ship these pre-built with the example instrument drivers, but it should be readily possible to use a BRAM based memory with the host API.

However, there are some examples that are also included in the distribution that do not use DRAM and do not use multiple clock domains to do so.  Since BRAM can be used at full rate (and can be made arbitrarily wide), you can run the BRAM at full speed with the rest of the acquisition engine.  You can find this in the "Simple" acquisition engine example under <LabVIEW>\examples\FlexRIO\FlexRIO Building Blocks\573X\Simple

These examples are better suited for some custom applications because the DRAM interface uses a lot of FPGA resources, and the "Simple" engine uses a push-based model which is more efficient than an on-demand fetch model.  However, it comes at a limitation that record sizes are constrained to what you can fit in a block RAM, and you don't have a lot of flexibility as to what you fetch and from where you fetch.

[RuchiG]

Awesome tool i used to syncronize two FlexRIO 7965R with 5781 adaptor modules. I upgraded to LV2012 and realised that there are some broken VI's. Is this going to get upgrade to 2012 soon?

[RolOrtega]

Hi,

Could you tell me which VIs are broken? I've been using the FlexRIO Instrument Development Library (FIDL) with LV 2012 for a couple of weeks now, and haven't seen any broken VIs.

There are a couple of things to keep in mind:

1) When you install FIDL, you need to point it to the right LabVIEW directory, it will not pick the newest one by default.

2) Right now, different versions of FIDL aren't completeley backwards-compatible. So if you installed the newest version of FIDL when you moved to 2012, that may be causing your VI breakage.

Let me know if that helps.

[dklipec]

If you are still using the FIDL 1.1 release, you would need to copy or reinstall the files to LV 2012.  However, the synchronization VIs will require the IPIN to be rebuilt with LV 2012. We plan on releasing an update soon for LV 2012, so you can choose to wait.  However, if you'd like to get started now, I've attached the synchronization VIs with the IPIN rebuilt.  You can just copy the files from LV 2011, or you can remove/reinstall the 1.1 library, pointing it at LV 2012 this time (the installer doesn't presently support multiple versions of LabVIEW).  Either way, you can just drop the attached files in:

C:\Program Files (x86)\National Instruments\LabVIEW 2012\instr.lib\FlexRIO\Libraries

... and have it overwrite the synchronization library.

[RuchiG]

Hi,

Thanks alot for the swift response. dklipec solution worked liked a charm. Only the synchronization library vi's were broken. I was suspecting it might have got to do with IPIN. Thanks a lot for the new synchronization library.

[KaiYang]

Hi

Is there any plan  to add 5771&5772 driver examples in FIDL? I find it much easier to implement a reference trigger with FIDL.

[peternu]

I'm using the example you provided and changed the triggering to PXI_trigger line as you showed in the video. I'd like to implement a continous acquisition. That is to say after each acquisition of all 4 channels of NI5734 of a predefined number of samples the FlexRIO should go automatically back and wait for another trigger from the PXI_trigger line. Thus no initiation of the acquisition should be necessary from the HOST (RT-target) after the first. The Host should allways read a whole record of the data without missing any.

Is there an example that you can provide?

What signal does the acq.Initiate input of acqEngineNRecordStateMachine expect? False, True, positive or negative edge?

Thanks a lot in advance

Peter