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Host Memory Buffer for CompactRIO

Hi Guys,

i have the same problem like Diego. Has anybody already solved that problem?

Thanks a lot .

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admin@NI-sbRIO-9637-030c9825:~# cd "/home/admin/RT Installer/"

admin@NI-sbRIO-9637-030c9825:~/RT Installer# ls

903x        906x        install.sh

admin@NI-sbRIO-9637-030c9825:~/RT Installer# chmod 777 ./install.sh

admin@NI-sbRIO-9637-030c9825:~/RT Installer# ./install.sh 906x

./install.sh: line 37: syntax error near unexpected token `newline'

./install.sh: line 37: `                done'

admin@NI-sbRIO-9637-030c9825:~/RT Installer#

----------------------------------------

Greetings from Austria

Andreas

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Message 11 of 19
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If you or whoever posted this code ( ) opened the shell file on windows, or some other situations (like using labview's functions) will cause this. If you have notepad++ and press the little button to show hidden characters, you may find some of the LFs got themselves CRs attached to them.

From the wiki https://en.wikipedia.org/wiki/Newline

If that isn't the case, then I'd just enter the steps in the script lines 49-51,54-56,60-65

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Message 12 of 19
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Hi smithd,

i already did that before what you mentioned. Thanks.

We have not found any special characters. I entered the steps manually which worked.

Now i have another problem. If i start the FPGA VI i see values for the AI0 on the frontpanel.

But in eclipse if i run the RT code i always get the value -1093125684. To generate the DO Pattern works.

I checked the signals with Virtual Bench it looks good.

Do you have any suggestions to make AI0 working. in Eclipse.


Thanks a lot

Andreas

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Message 13 of 19
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Honestly no, its been such a long time since I posted that I don't remember having any issues with the AI. Things that come to mind would be to just make sure its displaying the value in the correct type (the memory is U64s or whatever, I'm assuming the AI is FXP or SGL -- so make sure the code as posted converts it properly), verify no error is occurring when that particular register is looked up at the beginning (I'm pretty sure the code is set up to just die on any error ever, which makes it easy, but just double check -- I'm sure you've looked things up by name before yourself and had issues), and if you recompiled the bitfile at any point try rerunning the FPGA C header file generator thing and see if you get different register locations.

If none of those show anything up, I think you'll have to wait for assistance from the others (or pester them )

-Daniel

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Message 14 of 19
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Hi Daniel,

thanks for you fast response.

Yes it gets converted from FXP to U64. Which works correctly. With a Generator i send a

sinewave to AI0. If i also start the frontpanel of the FPGA VI i see the communication toggling which looks ok

and there i also see the right value for AI0 which is shown in the frontpanel and also gets written to the memory item.
(there are no error wires at the Register and Memory Items, so they should always get executed)

I think the FPGA VI is ok and running. Also think on RT side the most stuff should be ok. because the communication

statemachine is running continously and i can write data to the DO to FPGA. But the fpga.readHostMemoery(10) always returns 0.

I am not sure whow there values in the FPGA VI Frontpanel have to be set. What you see below are the default values.

fpga frontpanel.PNG

In the FPGA Code the AI Data gets written to the Register item.

ai to reg.PNG

And in the lower loop of the FPGA VI the Register Item will be converted and written to

the memory item at adress 10. (so the RT call hast to be "fpga.readHostMemoery(10)" right?
Are than the settings in my FPGA Frontpanel correct? I do not fully unterstand how to deal with

the "FPGA base, FPGA count, RT base, RT count" values.

reg to mem.PNG

Yes whenever i change anything in FPGA i run the FPGA C file generator to get the Bitfile with correct name and header file.

Copy both files to the C Project and to the Target. This has to be done every time. Otherwise i would get an error in Eclipse.

fpga error.PNG

Any other tips? I think it has something to do with the settings / numbers / adresses of the memory items?

Thanks a lot

Andreas

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Message 15 of 19
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If i remember correctly its one big memory block, so the first number (100) is the size of the block. Then I don't remember if they can both stomp on each other's data or if it has to be split like it is, but basically the other numbers are so RT and FPGA both agree on what segment of the memory block they are allowed to write to or read from. In this case the part of the buffer that the fpga is allowed to write to starts at index 10 and goes for 10 elements. In other words, yes I believe all those numbers are correct and that the AI is being written to the right place. If the RT side splits up the memory into multiple buffers (I don't think it does, but if...) then it might be read(0). If it works the way I think it does, read 0 should just return the first output from RT to FPGA, and read(10) gets the first input from FPGA to RT.

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Message 16 of 19
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Hello!

 

I'm trying to run the Host Memory Buffer example on a sbRIO-9651.

I've successfuly compiled the FPGA VI and now i'm having issues in generating the header file to compile the C program (with the bitfile shipped with the example it compiles and run but the program cannot load the bitfile, i suppose because it's a different target)

The FPGA Interface C API Generator gives a warning and does not output any file... I've tried both 2014 and 2015 version with the same result (i'm on LabView 2014 SP1) FPGA Interface C API Generator message

 

Any idea?

 

Thanks 

Stefano

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Message 17 of 19
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Hello all,

 

I'm trying to use Master Port / Host Memory Buffer on a PXI-8840 with PXIe-7822R / PXIe-7858R. The operating system is ETS (Pharlap), the LabVIEW version is 16.0f2 (32bit) / RT 16.0.0 / FPGA 16.0.0.

 

Does anybody know wether this is already available for targets other than cRIO / Linux?

 

Thanks in advance,

Joerg




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Message 18 of 19
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This appears to have been released at NI week 2017:

http://www.ni.com/white-paper/53881/en/

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Message 19 of 19
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