set an irregular external signal as 6733 sample clock
laconic
I want to generate anolog signals at some desired moment, such as 1V at 1ms, 2V at 2.3ms. My solution is that: generate sample clock in 7854R, rout the signal to PXI_trig1. Then I choose the PXI_Trig1 as my 6733 sample clock. I have three questions:1. how I should set the sample rate? 2. I find when the internal is less than 50us, the signal can't trigger the sample generation, why? 3. I want to generate 4 elements, but when I set the N of for loop 4, the sample generation can't finish completely. When N is 5 or larger, it does.
Hi laconic,
1. when you select the external clock as the sample clock, the sample rate is set to the the maximum expected rate of the sample clock.
2. what is the internal time? Is it the time between each elements? or is it the time between the 1V and 2V?
3. what do u mean "can`t finish"? Did it get less than four elements? How many elements do you get when you set it 5 or more?
1. The minum time step I want to achive is 2us, so the sample rate shoule be set as 500K?
2.sorry for the "internal time", it's "lasting time". It means that I want to make the 1V lasting 10us, so I creat a raising edge to trigger the 1V output and after 10us, another raising edge is created to make the 6733 output another value. In my time sequence, when the minum time step is mora than 20us, everything is ok. But when I want to get a 1V lasting 10us, or less, the DAQ error will happens(as error code -200018,as the picture displayed). I've been confused at this phenomenem for a long time.
3."can't finish" means that I get 3 elements. But the number of per channel in the task is 4, so the task can't finish and will wait until timeout occours. When I set it 5 or more, there are enough sample raising edge, but the goal number is 4, so I can get four elements successfully. What make me puzzled is that why four elements' generation needs five sample raising edge.
1. that`s right, but it maybe limit by the 6733. You can try some different value
2.this is the error reason:
The PCI bus uses Direct Memory Access (DMA) transfers by default to pass data from the DAQ board to PC memory. The PCMCIA bus is only capable of Interrupt Request (IRQ) data transfers which are less robust. Therefore, a PCI card is capable of much larger analog output and input operations. The PCMCIA bus limits the amount of data you can transfer acrosss the bus significantly. Unfortunately, the limitations are system dependent at this point in time. To reduce these errors, you must limit the use of the PCMCIA bus. If you have an applications generating these errors there are three options:
- )Use the on-board FIFO memory of the DAQ board to generate the analog output. The output will have to be periodic for each buffer interation, but the PCMCIA bus will now be eliminated for analog output. See the Related Links below for more information on "What is FIFO Mode Analog Output and How Do I Use It?"
- )Use an external instrument that you can control with serial or GPIB.
- )Use a DAQPAD (USB DAQ board), PXI, or PCI card
you can also find the solution in this link:
http://digital.ni.com/public.nsf/websearch/CC07E585D9F94D2B86256C1A005344EF?OpenDocument
3.can you firm the number of pulse that 7845 generated actualy? I think that it may be caused by hardware.
I think I get your point.
The reason is non-FIFO mode in my anolog outpu task. I want to generate an anolog output sequence which maybe has a very large data size(1M level), so I must choose the default non-FIFO mode, and then the maxium sample rate 6733 can achive will be much less than 1M and it depends on the CPU of the controller. That's right?
