Internal Logicanalyzer for debug purpose

[hagedornj]

Hello,

did anybody thought about an internal logic analyzer to debug internal target signals?

(similiar to signal tap from Altera or ChipScope from Xilinx). I have tried to use a FiFo for this task.

Maybe there are other solutions available?

Kind regards

Joerg

[David S.]

Hi Joerg -

Someone did indeed think of it!

http://zone.ni.com/devzone/cda/tut/p/id/10499

[BrowningG]

Hello Joerg,

It is possible to use ChipScope as an internal logic analyzer on your LabVIEW FPGA designs. Requests for this feature has been made a few times, so we created an example and tutorial on how to integrate ChipScope into your LabVIEW FPGA design. The bottom of this post contains information on where you can download the whitepaper and example, but I wanted to go over a few things first.

The example that is linked below creates a User CLIP core to hold the ICON and ILA cores necessary for a ChipScope design. By creating User CLIP for this example the ChipScope example is flexible enough to monitor LabVIEW FPGA logic, CLIP core logic, or to monitor the communication between the CLIP core and LabVIEW FPGA.

For most designs that use ChipScope, the ICON core will be instantiated as a dedicated component that directly connects to the JTAG pins on the Virtex 5. To simplify connection schemes, the JTAG port is not populated on LabVIEW FPGA targets. This requires that you use some of the dedicated DIO or GPIO lines on your FPGA target to serve as the JTAG pins. Since the ICON core directly connects to the dedicated JTAG pins, the ChipScope whitepaper includes a CLIP generator that connects your ILA core to a special version of the ICON core. This version of the ICON core is instantiated using normal Virtex 5 logic resources. This allows for you to instantiate your ChipScope design without having to use the dedicated JTAG pins on the device.

Download details:

You can download the ChipScope whitepaper here: Use Xilinx® ChipScope™ for On-Chip Debugging of LabVIEW FPGA Designs

The examples referenced in the paper are available here: On-Chip FPGA Debugging

If you have any feedback about the tool, please post it here. We are constantly looking for ways to improve the simulation and debugging of LabVIEW FPGA designs (especially ones that use CLIP) so we are very interested understanding how our customers want to use simulation in their designs. As part of that, what part of your FlexRIO design are you looking to debug?

Regards,

Browning G

[hagedornj]

Hello Browning,

up to now I have implemented two different types of debug features.

     1. Live check

     I am using a FiFo on the embedded side and a waveform viewer on the host side. It is very helpful to check if signals are coming or not

     2. OpenVeriFla (open source FPGA logic analyzer from opencores.org)

     With some modifications and a new UART module it was possible to implement the OpenVeriFla inside of the FPGA (OpenVeriFla Clip).

     The tools monitors signals and send the data via UART to the host PC. On the host side the data can be loaded into a verilog simulator.

Kind regards

Joerg