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Improve FPGA Design Productivity With the New LabVIEW FPGA IP Builder

Today, we announced the new LabVIEW FPGA IP Builder software, which incorporates high-level synthesis (HLS) technology to accelerate system design through increased abstraction. This new LabVIEW add-on enhances productivity by reducing the need for manual optimization of high-performance algorithms. Instead, users specify functional behavior along with design constraints and the software automatically generates a hardware implementation to meet requirements.

Product Features

•           Increased FPGA design abstraction for enhanced productivity

•           Improved algorithm performance and resource utilization

•           Separation of code and design constraints facilitates IP reuse

•           Seamless deployment to NI FPGA-based devices and integration with I/O

>> Learn more about the LabVIEW FPGA IP Builder here.