在 06-03-2009 09:39 AM
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在 06-03-2009 12:52 PM
是FPGA不能記憶9百多個數值??
最上方那張圖片,是使用97個delay,而下方網址 是使用9百多個delay。
http://tw.myblog.yahoo.com/jw!mzZdj.6AHxST_PYNzqJ3O6QEFW.R/gallery?fid=2
九百多個delay 程式網址 謝謝
在 06-03-2009 09:33 PM
我想製作一千個數值的delay,
如外接訊號量到
ex、1、10、5、8、9、2、4、3、12
取樣時間為1秒
假如我所以陣列長度4個
那每一秒陣列的數值為
[1 0 0 0]
[10 1 0 0]
[5 10 1 0]
[8 5 10 1]
[9 8 5 10]
[2 9 8 5]
[...........]
是否有半法能燒入compactRIO,且長度能到一千左右?
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在 06-03-2009 09:47 PM
Actually you don't have to worry about it. The number of LOCed IOBs simply means the number of I/Os reserved. You can refer to this link: LOCed IOB at 100% in LabVIEW FPGA VI Compile.
And I will asnwer the rest of your questions later.
在 06-03-2009 09:57 PM
目前LabVIEW版本無法知道。必須要compile 才知道。
在 06-03-2009 09:59 PM
這部分課程會介紹如何最佳化FPGA code, 建議上課
在 06-03-2009 10:16 PM
If your application takes a lot of space, and it requires more hardware components than that are physically available on the FPGA, the compile fails as always. And yes, 9 hundreds of register might be too many for it to complie. Besides, you should always limit using arrays and clusters (and their sizes as well) since they take too much space that would cause your compile to fail too.
I think that it is impossible to know how much space your application occupies before compiling (that's what compiling is for!). And you have to notice that it doesn't always have something to do with the size of your application, but rather what functions you use and the algorithm. So it's hard to tell before compiling. But you can try your best to do some optimization, such as avoiding using large arrays, large functions, front panel objects, etc.
If the sequence you are going to produce have a regular pattern, you can utilize your own algorithm to produce it, otherwise it might be somewhat hard to do it since it might take a lot of space.
在 06-03-2009 10:46 PM
照luvsocal所說,陣列數值定義太多,佔用太多空間,需要用演算法來產生delay當前的數值,
1、我是用外部訊號送入數值,無法使用演算法來產生delay當前的數值,如果使用演算法,那對於我所需求的功能就不同了。
2、1000個delay,所必需陣列1000個數,應該無法FPGA最佳化來解決。
3、如上圖網址,我所撰寫陣列所的程式,不知是否有改進空間,或是有更好的解決方法。
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