Having been stung trying to use HB's on a previous design, I was advised to use subcircuits instead. Now I'm working on a very large design and attempting to use subcircuits with and subcircuit bus connectors. For some reason it is very difficult to get the connections into the bus all named correctly. Even worse, after painstakingly going through and getting them all right and connecting the top level buses up to the subcircuits I find randomly spontaneous changes to the labels of bus entry connections through out my design. This makes no sense and is very frustrating. I'm on the verge of tossing a couple days work and wiring every individual signal without busses instead, even though the clutter will be horrendous. What's the story with this? Can bus connectors to subcircuits actually be made to work reliably? MS 11.0.1 Thanks.

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Multisim and Ultiboard

subcircuit bus connector problems

Author

Thanks for that tutorial.

You should add a section on how to deal with files that came from V10 to V11 with the 'netname' option selected. If you try to follow this tutorial and that has happened, you do not get the same dialogs you have shown, i.e. when connecting a net into a bus (dialog on pg 2).

Since you have moved to providing only the busline methodology you should provide a way to fix the legacy file within V11. I could probably re-instal V10 and open my file and change it and then bring it back to V11, but I don't think V10 can open the file anymore after it has been savedfrom V11.

Tien switched the mode on the file I had sent to tech support, but since I still continue to have problems with buses in that file, I have reverted to an older file and will not use buses into subcircuits. I just keep getting troubling bizzarre results, such as signals appearing in the wrong buses when I open the bus settings. Replicated subcircuits also keep coming up with bizzarre bus connector/netname assignments. I cannot spend more time on this, and cannot take the risk my design will be corrupted, so I will not use any bus subcircuit connectors. I will keep buses only on the top level, which so far seems to behave much more predictably.

I am also having problems with multisection parts in subcircuits that I will need to resolve with confidence before releasing this design. When I replicate a subcircuit many of the sections of a part are assign the exact same redes as in the original subcircuit, with a few given new refdes. I don't see how that cna happen, though I do know I need to manually re-integrate the section in each new replication. So far it seems to be fixable in that manner, though I am concerned I will get enexpected netlist errors as I have before that resulted in wrong layouts in UB. With these concerns it just seems to risky when also adding the issue of using bus connectors into subcircuits and how easily that can result in wrong connections.