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subcircuit bus connector problems

 

Having been stung trying to use HB's on a previous design, I was advised to use subcircuits instead.

 

Now I'm working on a very large design and attempting to use subcircuits with and subcircuit bus connectors.  For some reason it is very difficult to get the connections into the bus all named correctly.

 

Even worse, after painstakingly going through and getting them all right and connecting the top level buses up to the subcircuits I find randomly spontaneous changes to the labels of bus entry connections through out my design.

 

This makes no sense and is very frustrating.  I'm on the verge of tossing a couple days work and wiring every individual signal without busses instead, even though the clutter will be horrendous.

 

What's the story with this?  Can bus connectors to subcircuits actually be made to work reliably?

 

MS 11.0.1

 

Thanks.

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Message 1 of 11
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I notice that when I examine the signals in a bus, sometimes I see signals that are NOT part of the bus I am looking at, but are parts of other buses.

 

How can this happen?

 

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Message 2 of 11
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Aside from this behavior, maybe I am totally misunderstanding how buses work in MS.

 

It seems MS treats all buses as if they were one bus, even when named differently.  !!??

 

If I have a signal in one bus I cannot have a signal with the same label in another bus, even if the bus names are different.  This seems bizzarre to me since in many cases If I have data buses I want the bus names different, but to reuse the common splitter names such as D0, D1, ... for the bits in each bus.  I just am not finding any way to do this.

 

In the case of subcircuits with bus connections I want the names (or labels prefereably) internally to sometimes be the same, and connect to separately named buses externally at the top level.  This just does not seem to work.

 

Looking at the differences between connector labels and netnames I see in the help file that A splitter label and a netname can be different.  I just don't see anyway to do that in my current version 11.0.1.

 

If I open a bus I supposedly can rename a signal, but when I do it does not accept any name changes, just reverts to the old name where label still = netname.

 

If I add a signal to a bus via the properties interface it seems to work, and shows the signal in the bus as unconnected, but when I attach a splitter to the bus the new name I have added is not in the drop down list to choose.

 

Sometimes if I open a bus for editing, then when I close it it renames random buses in my design and changes the names of the bus splitter in many unrelated places.

 

Previous tutorials are obsolete as apparently bus and connector design methods have changed with recent version updates.

 

Is there something wrong with my installation? 

 

Is this how this is supposed to work? 

 

Is there a good current tutorial on buses and connectors and using them with subcircuits anywhere?

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Message 3 of 11
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dbur,

 

I would not want you to throw away your work if at all possible.  Can you create a Service Request for this issue so that we can directly address your problem with one of our AEs.

 

AIso I do beleive HBs and SCs are going to operate similar to each other (http://forums.ni.com/t5/Circuit-Design-Suite-Multisim/Nested-Subcircuits/m-p/1480840#M9394), although there are some minor differences on how the files are handled.

 

In the mean time, I will investigate busses and their use within HBs / subcircuits and will try to write up a general help guide on their use for the general community.

 

Regards,

Pat

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Message 4 of 11
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I'll try and get permission from the customer to post the file to your support group.

 

In this case I MUST use multisection components within subcircuits so I hope that issue doesn't burn me again.

 

Thanks.

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Message 5 of 11
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I have submitted the file and service request.  I'm reposting the text here since your web submittal form would let me put in enough characters.  It kept saying I was submitting moer than 2000 characters which just doesn't seem to have been the case.

------

 

I'm having numerous problems with buses, bus connector, signal splitters and subcircuits.

I have been given permission to share my file with you but it is considered highly sensitive information by my customer.  Each page has a confidentiality notice.

I have submitted this request related to forum discussion:
http://forums.ni.com/t5/Circuit-Design-Suite-Multisim/subcircuit-bus-connector-problems/td-p/1563458

For more detail please view that discussion since your web submittal page is not letting me put enough characters in here.

It seems MS treats all buses as if they were one bus, even when named differently.  !!??

If I have a signal in one bus I cannot have a signal with the same label in another bus, even if the bus names are different.  This seems bizzarre to me since in many cases If I have data buses I want the bus names different, but to reuse the common splitter names such as D0, D1, ... for the bits in each bus.  I just am not finding any way to do this.

In the case of subcircuits with bus connections I want the names (or labels preferably) internally to sometimes be the same, and connect to separately named buses externally at the top level.  This just does not seem to work.

Looking at the differences between connector labels and netnames I see in the help file that A splitter label and a netname can be different.  I just don't see anyway to do that in my current version 11.0.1.

If I open a bus I supposedly can rename a signal, but when I do it does not accept any name changes, just reverts to the old name where label still = netname.

If I add a signal to a bus via the properties interface it seems to work, and shows the signal in the bus as unconnected, but when I attach a splitter to the bus the new name I have added is not in the drop down list to choose.

Sometimes if I open a bus for editing, then when I close it it renames random buses in my design and changes the names of the bus splitter in many unrelated places.

In the design on the DIPB conn page there is a lone bus.  ADIPBLVDSbus  On one occasion I opened and renamed this bus, and it re-sequenced the net labels on all the other unrelated buses!!!??

Previous tutorials are obsolete, as apparently bus and connector design methods have changed with recent version updates.  I found the tutorials on new features of Ver 11.0.1, but they don't go into enough detail on renaming labels separately from netnames, or use of buses in subcircuits for me to see what I might be doing wrong.

Is there something wrong with my installation?

Is this how this is supposed to work?

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Message 6 of 11
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Hi Dbur,

 

 In V10, under Options>>Sheet Properties>>Wiring, there are two bus wiring mode  "nets" and "busline".  The nets mode is active in the file you sent to support and this is the cause of your frustration.  When this option is checked, the bus entry and the node will always have the same name and when you rename the bus entry on different bus using an existing name, what you are doing is virtually wiring.  The circuit below have a bus 1 and bus 2, but with the "nets" mode selected, R1 and R2 are actually connected together.

 

Bus.jpg

 

 

In v11, the check box is no longer available and you  have to use the busline mode. I don't know if you started the design in V10 and then brought it into V11, if this is true, your file will keep the net mode setting but now you don't have the ability to change to the busline mode.  If you started this design in V11 and this is happening, the only thing I can think of that caused this is the Multisim config file.  Delete your config file and see if you can replicate the problem in a new empty design.

 

I've changed the background settings in your file, please check you email.  


 

Tien P.

National Instruments
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Message 7 of 11
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I also looked for those settings and noticed I could not find them in V11.

 

I have a starter schematic with title and revision blocks and such things that I like to start with.  I probably used this to get the design going, so it's possible I carried through some settings from V10.

 

If you sent a file back to me I don't have anything in my email yet, other than the notice of this forum update.  When you say you changed the background settings does that mean you have fixed it to use busline mode?

 

Is it possible I could get to the correct V11 settings by starting a new design and copy and pasteing from the old schematic, or will that just continue to bring in the V10 settings?

 

Thanks.

 

 

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Message 8 of 11
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Hi dbur,

 

 Coping and pasting the schematic to a new page in V11 will work.

 We are having email problems, but check your inbox again.

 

When I say I changed the background settings, it means I changed the setting in the source code and it wasn't done in Multisim.  This is something that I

have to do for you.

 

Tien P.

National Instruments
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Message 9 of 11
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dbur,

 

Here is a document that I put together that should shed some light on how to best work with busses in Multisim - both in usage on a single page schematic and in a multipage or Hierarchical Block (HB) or Subcircuit (SC) basis.

 

Regards,

Pat Noonan

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Message 10 of 11
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