how fast can timed loop go?

[JingTY]

Hi all,

I am using a myRIO with Labview 2014 to acquire voltage signal at a high frequency.

I am just curious how fast can timed loop go for the data acquisition? The internal clock can run at 1MHz. Can my timed loop run at the same frequency to do data acquisition?

I wrote a simple program to display the intervals between two loops as shown below. But the minimium resolution it can give me is 1ms (1kHz) due to the limitation of the tick count VI. 

Is there a way to validate the loop frequency that is higher than 1kHz?

Thanks,

Tengyang

[crossrulz]

How are you aquiring the data?

If using a custom FPGA, then you don't need the Timed Loop.  You will need a While Loop to read the DMA FIFO that you are passing data from the FPGA to the host.

If you are not using a customer FPGA, then you are using the Scan Engine.  The rule of thumb for the Scan Engine is 1kHz rate.  If using a Timed Loop, you will want to set the timing source to be the Scan Engine clock.

[JingTY]

Hi Crossrulz,

I am still studying FPGA. I am using the scan engine method to acquire the voltage signal. 

Do you mean I can set the clock source type to "Synchronize to Scan Engine"? In this case, how fast can it go?

By the way, in the spec file, the aggregate sample rate of analog input is 500kS/s. Does that mean my device to take up to 500k samples per second in theory?

Thanks,

Tengyang

[crossrulz]

The general rule of thumb for the Scan Engine is 1kHz (1ms/update).  Going much faster will cause other processes to not be able to run.

That 500kS/s is how fast those AI can be read by the FPGA.  If you are using scan engine, you don't get that.  You will just get an update for each scan engine scan.

[JingTY]

Hi Crossrulz,

Thank you very much for your explanation. It is time for me to dig more into FPGA 😃

Best,

Tengyang