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How to decide the maximum number of elements for DMA FIFO in R series FPGA

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Greetings!

 

I'm working on a project with NI R series PCIe-7842R FPGA board. To achieve fast data transfer I'm using target-to-host DMA FIFO. And to minimize the overhead, I'd like to make the FIFO size as large as possible. According to the manual, 7842R has 1728 kb (216KB) embedded block RAM, i.e., 108,000 I16 type FIFO elements available in theory (1728,000/16). However the FPGA had compilation error when I requested such amount of elements. I checked the manual and searched online but couldn't find the reason. Can anyone please explain? And in general, what's the max FIFO size given the size of the block RAM?

 

Thanks! 

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I couldn't say exactly why this is the case, but it's likely because there is also information stored in those blocks about the FIFO configuration, data routing information, et cetera. If you're looking to minimize overhead, you should actually aim to use a FIFO on the smaller end anyway - provided you're reading from and writing to the FIFO at the same rate, this shouldn't be an issue for you.

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Hi scotia673,

Thanks for your reply. It makes sense that part of the block rams may be occupied by other processes. However I don't quite understand why a smaller FIFO would reeduce overhead? As I remember the overhead mostly comes from how many times data is transferred. Suppose I want to transfer 1MB data through DMA FIFO. Is it faster to do it at once or say 100KB each time for 10 times? Thanks.

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Accepted by topic author iron_curtain

Hey iron_curtain,

 

You are correct that moving larger blocks of data can lead to more efficient utilization of the bus, but that's almost certainly not the most important factor here. Assuming of course that the FIFO on the FPGA is big enough to avoid overflows, I'd expect the dominant factor to be the size of read performed on the host. In general, larger reads on the host lead to improved throughput, up to the speed of the bus. This is because FIFO.Read is a relatively expensive software operation, so it's advantageous to make fewer calls to get the same amount of data.

 

Note that the larger your call to FIFO.Read the larger the host buffer needs to be. Depending on your application, it might need to be several times larger than the read size. You can set the buffer size with the FIFO.Configure node.

 

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/ explains the various buffers involved. It's important to note that the DMA Engine moves data asynchronously from the read/write nodes on the host and fpga.

 

Let me know if you have any questions about any of this.

 

Sebastian

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