How do I make sure that the analog and digital output state of my FPGA card does not change after closing a reference?

[ColderAtom]

I am using an FPGA card  PCIe-7852R to provide digital and analog signals to control an experiment using Labview 2012 SP1.  I am doing bursts of DMA transfers of AO and DO values (and how long to hold each output state) from host to target.  The FPGA runs through the provided values and timing information. The FPGA must then hold its final output AO and DO values in between these bursts of rapid communication.  

To do this, I have built a state machine on the target side that empties all of the DMA buffers and maps to changes in physical output states of the AO and DO values.  The target then waits for a target front panel boolean to go true again (host does this)  before it rapidly repeats this sequence of reading DMAs and updating AO and DO output values.

Solution 0:

This partially works when the host vi follows the sequence:

While 

1   Open FPGA Reference

2    Configure DMAs

3     Start DMAs

4     Write to DMA's

5     Run

6     Set Target front panel boolean to True

7     Wait for Target to complete its reading of DMA buffers

8     Stop DMAs

9     Close and Reset FPGA Reference

End While

Problem 0: This fails because the close and reset (Line 9) changes the output state to its default value as I have read online.  This seems well documented online.

Solution Attempt 1:  I click on the Close VI (Line 😎 and select just Close, and think this ought to do it.  

Problem 1: Now however, the output AO and DO values do not update at all and some fraction of the time Labview just crashes.

Solution Attempt 2:  Only Open and Close reference at beginning and end.

1   Open FPGA Reference

Store FPGA reference in shift register

While 

2    Configure DMAs

3     Start DMAs

4     Write to DMA's

5     Run (on first iteratin of loop only)

6     Set Target front panel boolean to True

7     Wait for Target to complete its reading of DMA buffers

8     Stop DMAs

       Place same reference back in shift register

End While

9     Close (and Reset also applied and not applied) FPGA Reference

Problem 2: Again, the output AO and DO values do not change and some fraction of the time Labview crashes.  

I am concerned that even if Solution 2 were to work, the next time I run the host VI, I will Open a new reference and the output AO and DO FPGA values will reset to default values (there is no documentation I can find for what to expect.)  I could simply not close the reference at all and store it in a global or uninitialized shift register to be used the next time the vi runs, but my understanding is that when the host vi stops running the reference is Closed anyways.

I have tried many more solutions and variations, but these are the core spirits of the solutions I have tried over two days.  Any help would be greatly appreciated.

[Great_Britton]

Hey,

Would something like this work?

Have two loops on the FPGA side. One is waiting on an IRQ for the host to say it is ready to send data. Then it retrievs the data and sets a flag saying it has new data.

The other loop is continuously outputting data stored in shift registers, and checks a the new data flag every iteration. If the flag is set, it overwrites the data in the shift registers with the data recieved from the host.

On the host side, don't close the FPGA reference in-between communicaiton bursts, just store it in a shift register, and you probably don't need to stop the DMA. Putting DMA timeout handling in the FPGA code might be a better option. (for instance, you could have it trigger an IRQ and wait for a response from the host if the DMA times out).

[ColderAtom]

Thank you so much for your response.  Given your response, it seems like my soln 2 ought to work.  Since it isn't, maybe it means there is a bug in my code that I just keep missing.  Two questions though:

(1) Do you know if Opening a new VI reference changes the output state of the AO and DO channels?  I am worried about stopping and starting the Host side vi causing the AO and DO values to reset, since it appears that stopping the host VI closes any references that were open.  Is there any documentation on this?

(2) Is there any harm or additional overhead associated with stopping the host to target DMAs, reconfiguring their depth to match that of the new stuff I want to do, and then restarting them?  Doing this greatly simplifies the code on the host side and reflects that the type of application this is being designed for involves 1 second of lots of FPGA activity, followed by 1 to 100 seconds of waiting.

Any help you can provide would be great.

[Great_Britton]

Hey,

Opening or closing an FPGA reference has no effect on the FPGA. Only executing commands and methods, like "Run" or "Download" will affect it. 

There shouldn't be any harm in configuring the DMA FIFO's that way, although it might be easiest just to leave the set at the largest depth you need, and then communicate to the FIFO how much data it should retrieve from it. To make sure the implementation you choose is fast enough, you can always just include some benchmarking in the code and try it out.

[ColderAtom]

OK.  So here is an explicit answer for anyone else who has this problem one day.

(1)  When the FPGA VI Reference is created:

         Right click on Open FGPA VI Reference

         Choose to configure

         Uncheck the box "Run the FPGA VI"

(2) When closing the FPGA VI Reference

         Right click on Close FPGA VI Reference

         Select "Close"

This does this trick.  I had step (2) correct, but missed step (1).  Because my DMA's were not loaded and running it caused the running of the Target VI to fail and leave the DO and AO in with all zero voltage outputs rather than their values just before step (1).