9503 Stepper Velocity control: drive disables automatically

[Rhishi]

Hi,

I'm playing around with NI 9503 Stepper Motor Drive, cRIO-9068, and ST23-4E NEMA 23 motor. I began with the example project that ships with LabVIEW 2015 for Stepper Motor Velocity Control using 9503. The motor runs fine with that example code. Next, I wanted to make my own alternative implementation of the control loops. So I took the example code, and modified it.

But the motor refuses to run after my modifications. I'll soon furnish the details of my modifications. Quick summary is: I'm using a different approach to timing the I/O. And for that, I've my own PWM generator block.

But before going in the details, I wanted to ask if there are any common reasons of the symptoms I'm seeing:

When I enable the drive, and lower the reset line, the motor gives one quick jerk, and the drive disables itself automatically. It does not indicate any fault, and the status reads "Disabled by software".

Here are more detailed observations:

Step 1: enable = false, reset = true: everything is running fine. I see the default PWM duty cycle values of 0.486389.

Step 2: enable = true, reset = true: still everything fine. PWM duty cycles are still at default 0.486389.

Step 3: enable = true, reset = false: PWM duty cycles wiggle from the default, one quick jerk of the motor, and drive is disabled automatically to "Disabled by software".

I looked up the timing requirements of 9503 listed in LabVIEW >> Help (here's the online version). I saw that the PWM should have minimum pulse width of 200 ns. I modified my PWM block accordingly. Also, there is a statement saying "Wait at least 1 µs after a phase change before reading the current." I could not figure out what that means. What is the phase change? The advice to refer to 9503 Timing does not help, as it does not talk about the 1-us-after-phase-change constraint.

Also, speaking of timing, how important is it to sample the currents at the center of the PWM pulses? I mean, how accurately is "at center"? Given that the current reading node takes 18.5 us, and the PWM period is 50 us, if I fire the current reading node at t = 25 us, when does the current sampling actually occur between [ 25 us, 25 + 18.5 us ]?

Thanks

Rhishi 

[PaulRB]

It's going to be very difficult to get the 9503 to work with your own PWM generation block. There is very precise timing between the current loop and the PWM generation loop that will no longer happen if you use your own PWM generation code. If you post a VI I can take a look at it and try to find the areas that could be causing issues.

When you run the IO node, the sampling happens almost instantly (there might be a ~300nsec delay). What takes 18.5 usec is to get the data from the 9503 back to the FPGA.

[Rhishi · Accepted solution]

I was going to clean up and post my VIs, but then I found the error. My implementation was sampling the current at the center of the high pulse, but they should be sampled in the center of the low pulses. I discovered that after simulating the outputs of nism.pwm.vi and nism.pwm.2.vi blocks. See my simulation waveforms below. Note that I've plotted the falling edge transitions of the Trigger output.

Too bad the documentation on the PWM blocks isn't quite precise about this. It says this about the trigger:

Trigger—Returns TRUE at the middle of the high portion of the PWM period and falls to FALSE after 50% duty cycle. Use this output to notify the current sensing code of the correct time to sample the current.

That is a confusing line of text after seeing the waveforms. One interpretation is: "PWM Period" is [0, 2000], [2000, 4000], etc. in the waveform. Trigger returns TRUE in the left half of the PWM Period (not "at the middle of the high portion" -- I don't know what that means -- how wide is "middle", what is exactly the "high portion"?). Trigger returns FALSE in the right half of the PWM Period. The actual PWM pulses are center-aligned at P, 2P, 3P etc. i.e. they span the intervals [P/2, 3P/2], [3P/2, 5P/2], and so on. That means they are phase-shifted by P/2 w.r.t. the PWM Period.

Or I could just phase-shift what I just wrote: there is PWM Period = (1/frequency) * clock tick. You get PWM pulses such that centers of all high pulses are exactly at the centers of PWM Periods. Trigger makes a falling transition at the start of the PWM period, and it makes a rising transition at the center of the PWM period. You can use these two transitions to trigger your current sampling at center of either low or high pulses respectively. New duty cycle is latched at the beginning of each PWM Period. The first PWM Period starts after a delay of Period/2 after reset goes low.

The documentation tries to draw waveforms to explain what center-aligned and left-aligned means, but skips drawing trigger waveform and sampling events in that diagram. I wish it didn't skip.

And oh, I wish the 9503 module documentation or example code had a big banner saying "I live on center-aligned PWMs, and if you want to ask me for my current reading, please ask at the center of the low pulses."