FPGA BCGLookup VI

[ChristopheC]

Hi,

Here is an example that shows how to get the results from the Histogram back to the host.

Basically, you have to create a Target to Host DMA FIFO, and use it to send the histogram data when the output valid is true.

On the host side, after reading the image back from the FPGA, read the 256 elements that were written to the FIFO (I wrote the code for a 8-bit image).

I also added the BCG Lookup, so you can see that the Histogram changes when you change the BCG values.

The top loop detects changes in the BCG value and when they occur, set the value on the FPGA side.

For this example to work, you're going to have to edit the properties of the cRIO to enter the IP address of your target, and compile the bit file.

Hope that helps.

The mask version is very similar, you have to create a Mask image, and send it to the FPGA, just like you send the source image to process. The mask image can be created using IMAQ ROItoMask. The rest of the code should be the same.

Hope this helps.

Christophe

[dalyto]

yeah thanks very much it is very helpful for me

and when i want to used the color histogram it's just i change U8 to U32 for RGB32 pixels or HSL32 pixels 

thanks again 

why  used the the histogramFIFO configure and what you mean by Requested Depth = 1024 ???

and if i want to safe the image  from  FPGA after the BCG Lookup how ?? because when i try to put the image in global variable or save in file bath i can't the image is empty or the programme show me message errors imaq vision image type not valid it is not image 

thanks  again im not good in vision FPGA 

[ChristopheC]

> why  used the the histogramFIFO configure and what you mean by Requested Depth = 1024 ???

FPGA DMA FIFOs have a double buferring mechanism. When you declare the FIFO in the project (on the FPGA target, you request a number of elements, which is the depth of the FIFO on the FPGA.

When you initialize the FIFO on the host side, you can specify another sise, which is the depth of the FIFO on the host.

As a general rule, you usually want to keep the default on the FPGA side (as increasing the size will use more resources), but you can increase the depth on the host side. Allow for a size big enough so you can dequeue the elements fast enough so that the FIFO does not overflow.

In this case we enqueue 256 elements on the FPGA side (size of the histogram) before the data is sent back. I allowed for 3 times more.

You need to set the size also based on how fast you're going to read the elements on the host, knowing the difference between your FPGA processing time and transfer time, compared to your loop rate on the host.

If there is some bottleneck, this is when the 4-wire synchronization signals come into play: If you don't read the elements fast enough on the host and the queue gets full, the FIFO.Write method on the FPGA VI will let the previous VIs know that it is NOT ready for input.

This is going to propagate all the way to the Read Pixel VI and the pipeline is going to stop until the queue is not full and can accepts more elements.

As for saving the image, one thing to be aware of is that the Image datatype is by reference in LabVIEW, not by value.

This means that you want to make a copy of the image in a new image in the display loop and you want to save that copy in loop where you handle the UI controls.

I modified the host VI to show you how to do that. If you already compile the FPGA VI yesterday, you should not have to do it again.

Hope that help,

Best regards,

-Christophe

[dalyto]

thank you a lot

but why the type of histogram is FXP (fixed point data) not cluster of histogram values because i need the mean value of histogram to compare with min and max value ??

it is not the same like host 

 

[ChristopheC]

Hi,

This application note answers your question:

http://digital.ni.com/public.nsf/allkb/80C9808E454DCBC286257093005B9EB6

So instead, we chose to return the array elements one by one, letting the user know when they're ready using the Output Valid signal.

Hope that makes sense.

Christophe

[dalyto]

HI

So they are no solution to get the  mean value of histogram and also with the vsion  assistant  in FPGA  i can't use the interval Range to specifying the minimum and maximum boundaries for the histogram calculation

because in my project i want to get the mean value to compare with other mean value 

this is worked in RT very easy but when i want to do this in FPGA  i think is not workable

[ChristopheC]

The Mean is not returned directly by the Vision Assistant Express VI on the FPGA side. Also, Vision Assistant does not expose the range input, but if you want to have access to it, you can compute the Histogram outside of Vision Assistant using the NoMask withRange U8x1 instance of the VI.

The FPGA Histogram VIs only returns the histogram values for each gray level. But it is possible to compute the mean "manually" either in the FPGA VI, or on the RT side once you retrieve the complete array.

You just have to write a bit of LabVIEW FPGA code to do it on the FPGA side.

[dalyto]

i don't  understand you  if the  FPGA Histogram VIs only returns the histogram values for each gray level

how is possible to compute the mean "manually" either in the FPGA V ??? im sorry I am a beginner in labvie FPGA

[ChristopheC]

Well, you program it in LabVIEW, based on the values returned by the histogram function. If you want to compute it on the FPGA, you have to accumulate the data since the FPGA histogram VI returns one value at a time at each iteration of the loop.

Whenever a histogram value is valid, you multiply it by the corresponding gray level, add that to the previous value, and you're done when you've gone through the 256 gray levels. You then divide the result by the size of the image and you have your mean.

See attached code. As I explained in my previous message, I showed how to compute it on the FPGA side (I added a subVI to compute the sum, that I then divide by the image size), and I also showed how to compute it from the histogram array that we get back on the host.

I would recommend you study some of the the simple LabVIEW FPGA examples provided with LabVIEW to see how things are done in LabVIEW FPGA. You typically get a single data at each new iteration of the loop, and you have to use feedback nodes to do simple operations like adding the elements you're getting at each iteration. It's a different programming style and mindset than standard LabVIEW because FPGA is a streaming architecture.

So yes, it's a bit more difficult. There is some learning curve.

Hope that helps.

Best regards

Christophe

[dalyto]

thanks very match 

now i used this apllication with  Smart camera NI-1742  but i have problem in smart camera i can acquire image but i can't send for FPGA target from Smart camera