08-11-2015 12:38 PM
Hi all
I'm trying to re-design a vendor's FPGA code to change a camera from 4x12 Medium to 8x8 Full.
The Camera Link standard is pretty confusing. The way I read it, a Camera Link Full 8x8 camera should assign the Valids as follows:
LVAL: bit 24 on all three channels
FVAL: bit 25 on all three channels
DVAL: bit 26 on all three channels
For some reason, the vendor asigned them like this (and IT WORKS!):
LVAL: bit 18 on all three channels
FVAL: bit 19 on all three channels
DVAL: bit 20 on all three channels
Is there another format that this Valid Bit arrangement matches? If so, is there something in the Camera File Generator and .ICD files that sets the format?
Cheers!
MADman
Solved! Go to Solution.
08-11-2015 03:02 PM
MADman,
Yes, you are correct that the LVAL, FVAL, and DVAL are on TX/RX24, 25, and 26 respectively. These bit assignments correspond with the parallel interfaces on the Channel Link Serializer/Deserializer Chips. The PCIe-1433 will expect that the framing signals are mapped to these signals at the camera.
Not all cameras output a DVAL signal, so these can be ignored in the frame grabber (PCIe-1433) with a camera file setting. Additionally, the polarity of the framing signals can be inverted with a camera file setting as well.
You may be interested in using the Camera Link Logger application along with the PCIe-1433 to capture the signals from the camera. The camera link analyzer will present the camera link signalling in an easy to read visual format that may help your development/debug.
http://www.ni.com/product-documentation/14301/en/
Regards, Jeff
08-11-2015 03:14 PM
that's pretty slick, Jeff. I don't want to update the LV version on the eval system PC, because I want to always be able to get back to the vendor's setup. However, my office PC has LV 2014 installed, so I might try moving the 1433 into my PC and installing this CL Logger. I might even get the boss to buy another 1433.
Thanks for the tip!
MADman
08-14-2015 01:46 PM
Hey everyone
So the thing that was messing me up was the fact that the Camera Link / Channel Link pins don't line up with the bit assignments in the serial channels. Maybe that was helpful for board layouts in designs using Channel Link chips - but for someone designing Camera Link modules in an FPGA, it's pretty damn confusing.
Attached is a little spreadsheet I made up mapping Camera Link serial bits through the 'Ports' to up to (8) 8-bit pixels. I don't see why anyone should waste as much time as I did getting this straight. NOTE: you'll have another level of scrambling to do if you're doing 10- or 12-bit Camera Link designs.
I need to do the same exercise for an 80-bit configuration that is the eventual target. I'll try to remember to post that spreadsheet once it's done.
Cheers!
MADman