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1473R FPGA

Hı all
I m using 1473R card with basler camera.
I have some questions about vision assistant on 1473R examples in labview fpga.
This program uses 100 MHz clock with SCTL when writing to DMA for image reading. My question is how I can redesign this code to work at 40Mhz with SCTL. I tried changing all clocks with SCTL but control IO errors occur. This IO control works at 100Mhz message comes. Thanks for your replies.
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Message 1 of 6
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I would recommend going with the default 100 MHz clock. Is there any particular reason that you are need to use the 40 MHz clock. I have a couple questions for you:

 

What errors are you receiving when you change to the 40 MHz clock?

What example program are you using?

Would you please post pictures of the modification that you made?

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Message 2 of 6
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Thank for reply. I am trying to detect particles(bright small objects) in video images in real time. Labview FPGA has an example “İmage Processing with vision Assistant on 1473R (FPGA) Project file.”. in this vi I used threshold and particle analysis report in vision assistant. Bu when I started to compiling “timing violation error “ happens and “4.36 ns missed” warning comes. I examined timings at compiling tables and approximately 14.36 ns is necessary for this problem. 100Mhz SCTL (10 ns) seems not sufficent for this problem. So ı decided to change 100Mhz to 40Mhz (25 ns). I think this timing will be enough to detect particles. When I changed all 100Mhz SCTL’s to 40Mhz SCTLs in this vi ı received an error. “Cl port A, Cl data valid , Cl output valid can be used at 100Mhz İmage data clock”. I coldn’t solve this problem. Also I tried to form another 40 Mhz SCTL parallel loop in this FPGA vi. But I take overflow error . Also Labview FPGA has another example “ Particle analysis report on FPGA “. I looked this vi. But this vi reads one image not a video and works at 40Mhz SCTL. How can I detect particles(areas, centroids) with FPGA and camera link camera (at 1473R card). Thank you very much.

error.pngImage Processing with Vision Assistant on1473R.png

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Message 3 of 6
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Hi impect,

Most Camera Link cameras transfer data on a pixel clock that usually runs at 80 MHz. The pixel clock pulse tells the FPGA when a pixel is arriving. See Figure 3 here.

 

It is important to understand that the camera is controlling the data transfer. So the camera tells the FPGA "here's the next pixel" based on its own internal clock pulse that is read by the FPGA. The FPGA cannot say "okay, I'm ready, give me the next pixel", it must be ready and able to detect the pixel on the camera's pixel clock when the camera sends it.

 

The FPGA loop that acquires image data from your camera must run at a speed faster than the camera's pixel clock, or it will miss pixels. This is why you get an error when changing the acquisition loop to 40 MHz.

Since your image processing needs cannot be performed in a SCTL at 100 MHz, you have two options:

 

1. You can reduce your camera's pixel clock to 40 MHz if your camera allows for you to modify that setting. Note that this will reduce your maximum image acquisition rate proportionally.

2. You can move your image processing to another loop running at a different rate. 

 

Essentially you would write your pixel values to a target-scoped FIFO inside the acquisition loop, and read them out in a separate loop for processing. Keep in mind that if your image processing takes longer than your image acquisition, you will miss frames, and will have to take care that the image FIFO is cleared in pace with acquisition to avoid overflow.

 

Alternately you could write your image array to a local variable in the acquisition loop and read it out in the processing loop.

See these resources for more information and transfering data between different clock domains:

http://www.ni.com/documentation/en/labview-comms/1.0/fpga-targets/transferring-data-clock-domains-fi...

http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/implementing_domains/

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Message 4 of 6
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Hi impact,

I want to add to what grae323 is writing.

Camera link chip on the NI PCIe-1473R needs to operate in 100MHz clock rate.

You can't change that.

Your processing loop that takes the data out from the FIFO can process in any speed that is a good fit to the camera speed.

For example my camera runs in 40MHz on the camera link.

So I run the image processing in 60MHz.

Amit Shachaf
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Message 5 of 6
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I see also that you attempted to read out the pixels for processing in a separate 40 MHz SCTL but encountered an overflow error.

Your acquisition loop is writing pixels to your FIFO buffer at 80 MHz (the camera pixel clock), but you are reading them out at 40 MHz. This means that while an image is being acquired and transfered, pixels will be building up in your FIFO. You need to configure this to be large enough to not overflow during transfer (right click to configure FIFO size).

Additionally, you need to make sure that all the pixels from one image have been read out in your processing loop before the next image is ready to be acquired in the acquisition loop, or your FIFO will overflow regardless of its size because you will never be able to pull pixels out faster than you put them in. The max acquisition rate is 40 MHz divided by your image resolution, because this is as fast as your processing loop can read out an image (one pixel per SCTL at 40 MHz).

You could avoid this problem by configuring your camera to run on a 40 MHz clock, as AmitShachaf suggests, ensuring that pixels are written to and read from the FIFO at the same rate.

 

Or, slow your image frame rate so that the processing loop has enough time to unload each pixel at 40 MHz from the FIFO before it's time to acquire the next image. Pixels will build up in the FIFO during a frame acquisition, but will all be read out by the processing loop before the camera starts sending the next image.

 

Or, use a boolean to decide in the acquisition loop whether to write the current frame to the FIFO or not, and set this to true in the processing loop at the end of each frame pull from the FIFO, etc. You will miss frames if your acquisition is faster than your processing.

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Message 6 of 6
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