Trigger off rising edge of line being read

[Sneaker]

The device I am using communicates via BiSS-C. Similar to SSI. From the time that I start generating clock pulses on the master clock there is a varying window of time that the board will take to start sending back data. The SLO idles high and then drops low as it is calculating the data to be sent back. Then the first two bits in the word are 1 then 0. Is there a way to trigger off of the rising edge of that SLO digital line I'm reading? I am using a PXI-6289.

[AlexAlligator]

Hello Sneaker,

I haven't worked with BiSS-C or SSI before, but Page 99 of the M Series (DAQ) User Manual (linked here) describes a method which should prove useful for this task. Also see our 'Digital - Finite Input.vi' example which has 2 digital trigger options for reference. (Edit: I had forgotten that this is a LabWindows/CVI thread; I'll try to find an example for CVI.)

[Sneaker]

Coincidentally, that's how I ended up doing it without actually having referenced that doc. I did admittedly "cheat" though. BiSS-C and SSI has that acquisition period that can very. I ended up just tossing the samples within that period and doing some bitwise operations to get the valid data.