LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

will parrallel loops running in my real time code, conflict when they both call my FPGA code?

Thanks guys, I am going to use the code, but also do some reading up.

 

Thanks again,

0 Kudos
Message 11 of 12
(228 Views)

Hi,

I am not an expert on FPGA, but I dont think there will be any conflicts. Because the two loops are actually not communicating with the FPGA subvi, but the the program that is being executed in the FPGA hardware.

If this FPGA code were just a subvi (which is not clone), and two parallel loops were accessing it, there might have been some conflict or race condition.

But in case of FPGA, physically there is a circuit being created. I read somewhere that separate registers will be allotted for different front panel items. The parallel loop(ie, the RT controller) should be able to access these registers without any conflicts, as long as same front panel item is not accessed at the same time from two loops. For DMA also, I believe there will be separate channels created.

0 Kudos
Message 12 of 12
(219 Views)