I write an VI on a PCI-7811R FPGA card, as a test.
The attached pictures show the VI and the compile result.
I just want to write TRUE or FALSE into 5 pins in a STCL loop,in which I set the clock at 200MHz .
After compile, the result says:
Base Clock
Requested Rate: 40.408938Mhz
Theoretical Maximum: 351.493849Mhz
Derived Clock:
Requested Rate: 202.061122Mhz
Theoretical Maximum: 208.681135Mhz
I'd like to know what does this 208.68Mhz mean?
does it mean that it could complete the loop 208.68M times in one second(5ns for one loop) ?.
Then what does the Theoretical Maximum: 351.493849Mhz mean?