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what does this compile result mean on an FPGA program?

I write an VI on a PCI-7811R FPGA card, as a test.
The attached pictures show the VI and the compile result.
I just want to write TRUE or FALSE into 5 pins in a STCL loop,in which I set the clock at 200MHz  .
 
After compile, the result says:
Base Clock
Requested Rate:              40.408938Mhz
Theoretical Maximum:     351.493849Mhz 
Derived Clock:
Requested Rate:              202.061122Mhz
Theoretical Maximum:     208.681135Mhz 
 
I'd like to know what does this 208.68Mhz mean?
does it mean that it could complete the loop 208.68M times in one second(5ns for one loop) ?. 
Then what does the Theoretical Maximum:     351.493849Mhz  mean?
 
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In 7811R, FPGA has a 40MHz base clock, you can use multiple and divide to get higher frequency. You can set it by right click the 40MHz clock in Project. After you set it, you can use it in timed loop and it can execute at this speed.
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Well, FPGA's are not that transparent... What I understand is this.

The FPGA uses slices. Each slice takes some time to execute. This time is
*not* a clock cycle. In one cycle, the FPGA can execute many slices, even if
they depend on each others output. For instance, you can put a few math
functions (add, subtract, etc.) behind each other, and still execute it in
one Single Cycled Timed Loop (SCTL).

When you increase the frequency, the base clock increases. But the execution
time of the slices doesn't. So the idea that increasing the clock time
simply speeds up the FPGA is wrong! This does work on "normal" processors,
but not on FPGA's.

So if you get your code in a SCTL running on 40 MHz, you might get failure
when you run it on 200 MHz. This is because the base clock is running faster
(so the SCTL is faster), but less slices can be executed in that time!

In your case, the executed slices will still fit if a base clock cycle is a
bit shorter. This is not possible, since the FPGA cannot create a 208 MHz
clock, so it is theoretical.

Hope it helps,

Wiebe.


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