ways of synchronizing PXI fpga clock

[tom_ifms]

It seems that there are two different ways of synchronizing the code on the PXI 7852R to the clock of the PXI-1062Q chassis. What is the difference:

1.

As described in http://digital.ni.com/public.nsf/allkb/D108D4AF937524CA862570FF004C2A48?OpenDocument

I'm not quite sure what this actually does: I have a 40 MHz onboard clock on my fpga; is that the one that will be synchronized? Will thus the 10 MHz chassis clock automatically be multiplied to 40 MHz?

2.

Use a single cycle timed loop and choose the chassis 10 MHz clock (or a derived clock from it) as the loop clock

What is the difference between these to ways? What does the first way do exactly (does it also apply to untimed loops)?

[CarstenS]

Hi tom_ifms,

the first methode synchronizes your 40 MHz clock to the 10 MHz PXI clock. With the second methode the SCTL uses the PXI clock directly.

Hope this helps

Kind regards

Carsten