too much device utilization & compile time

[110208004@kocaeli.edu.tr]

hello everyone

I wrote a basic program for myRIO as FPGA target. I use just a button and a led. But it takes 40 minutes to compile it and it says that it uses 44 percent of the fpga. I think it is impossible how is it possible i dont have any other code on the project.  Actually my program works correct with no problem. But it is not logical. I use sbRIO too there i have meaningfull results as device utilization

I have installed LabVİEW 2013 for myRIO, LabVIEW FPGA, LabVIEW Compile Farm 2013 and LabVIEW Xilinx Tool. Is there any other software needed ? 

Can anybody say something about this

[P@Anand]

It really sounds wiered. So are you sure that no other source file components are added in the build? Can you show the Compilation Summary ?

[Luis32]

Hello

I think there is no much information to answer this but I can tell you that it is normal the time that is taking. If you have a very small program it can take 15 minutes and by increasing your program, the amount of time that it will take to compile will also increase. This is because the program have to be used by the xilinx tool and this works very slow.

Also about the memory, sometimes this can happen, if you use DMA's they are going to take a lot of memory. You need to consider the amout of DMA's available on your device and how many of these you are using. If you have in the front panel a button and a led, that is not going to fill your memory much because they are designed to be used on the fpga and not to take much resources. If you can notice, there is going to be only very simple images for the fpga front panel and this is the reason why.

I hope this can clear some things for you.

[T-REX$ · Accepted solution]

The MyRIO uses a similar zync chip to the NI 9068 CompactRIO. See here for more info on why you're seeing this behavior: http://forums.ni.com/t5/LabVIEW/cRIO-9068-FPGA-high-device-utilization/td-p/2825138

[110208004@kocaeli.edu.tr]

the answer from T-REX$ here sounds true. I accept it as right answer. Thank you  T-REX$.

cade for you i add a compilation summary snip. this time it takes 19 minutes. You can look at device utilization. 

[110208004@kocaeli.edu.tr]

T-REX$ is it okay with the device utilization that i send in the previous post ? 

[110208004@kocaeli.edu.tr]

T-REX$ what can u say about this I'm using zynq XC7Z010. 

I add another picture.

I'm looking at this . page 3 and 5 can say something to us

[T-REX$]

Hey 110208004@kocaeli.edu.tr,

That appears normal to me. In the other thread I linked you to, Lucian got very similar results for his simple VI. His VI was slightly more complicated than yours, so that explains why your resource utilization is a little bit lower.

Your results are on the left, his on the right.

[110208004@kocaeli.edu.tr]

T-REX$ thanks a lot to you. Everything is all right than. I often use ISE and Verilog to programm FPGA. There i have not such as this results for zynq FPGA's by device utilization. 

Thanks for your help again